linux-kernel - Re: [PATCH 5/6] x86: mm: new tunable for single vs full TLB flush

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Message-ID: <53BB3EBC.8050005@linaro.org>
Date:	Tue, 08 Jul 2014 08:43:40 +0800
From:	Alex Shi <alex.shi@...aro.org>
To:	Dave Hansen <dave@...1.net>, Mel Gorman <mgorman@...e.de>
CC:	x86@...nel.org, linux-kernel@...r.kernel.org, linux-mm@...ck.org,
	akpm@...ux-foundation.org, kirill.shutemov@...ux.intel.com,
	ak@...ux.intel.com, riel@...hat.com, dave.hansen@...ux.intel.com,
	"H. Peter Anvin" <hpa@...or.com>
Subject: Re: [PATCH 5/6] x86: mm: new tunable for single vs full TLB flush

On 07/08/2014 01:43 AM, Dave Hansen wrote:
> On 04/24/2014 03:37 AM, Mel Gorman wrote:
>>> +Despite the fact that a single individual flush on x86 is
>>>> +guaranteed to flush a full 2MB, hugetlbfs always uses the full
>>>> +flushes.  THP is treated exactly the same as normal memory.
>>>> +
>> You are the second person that told me this and I felt the manual was
>> unclear on this subject. I was told that it might be a documentation bug
>> but because this discussion was in a bar I completely failed to follow up
>> on it. 
> 
> For the record...  There's a new version of the Intel SDM out, and it
> contains some clarifications.  They're the easiest to find in this
> document which highlights the deltas from the last version:
> 
>> http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developers-manual.pdf
> 
> The documentation for invlpg itself has a new footnote, and there's also
> a little bit of new text in section "4.10.2.3 Details of TLB Use".
> 
> The footnotes say:
> 
> 	If the paging structures map the linear address using a page
> 	larger than 4 KBytes and there are multiple TLB entries for
> 	that page (see Section 4.10.2.3), the instruction (invlpg)
> 	invalidates all of them
> 
> I hope that clears up some of the ambiguity over invlpg.
> 

Uh, AFAICT, the invlpg on large page has no clear effect on data
retrieving, on all Intel CPU till ivybridge. No testing on later CPUs.

-- 
Thanks
    Alex
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