linux-kernel - RE: [PATCH V3 1/2] perf ignore LBR and offcore

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Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077014CDF76@SHSMSX103.ccr.corp.intel.com>
Date:	Tue, 8 Jul 2014 14:22:25 +0000
From:	"Liang, Kan" <kan.liang@...el.com>
To:	Peter Zijlstra <peterz@...radead.org>
CC:	"andi@...stfloor.org" <andi@...stfloor.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"kvm@...r.kernel.org" <kvm@...r.kernel.org>
Subject: RE: [PATCH V3 1/2] perf ignore LBR and offcore_rsp.



> -----Original Message-----
> From: Peter Zijlstra [mailto:peterz@...radead.org]
> Sent: Tuesday, July 08, 2014 5:29 AM
> To: Liang, Kan
> Cc: andi@...stfloor.org; linux-kernel@...r.kernel.org; kvm@...r.kernel.org
> Subject: Re: [PATCH V3 1/2] perf ignore LBR and offcore_rsp.
> 
> On Mon, Jul 07, 2014 at 06:34:25AM -0700, kan.liang@...el.com wrote:
> > @@ -555,7 +577,11 @@ static inline void __x86_pmu_enable_event(struct
> > hw_perf_event *hwc,  {
> >  	u64 disable_mask =
> > __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
> >
> > -	if (hwc->extra_reg.reg)
> > +	if (hwc->extra_reg.reg &&
> > +		((hwc->extra_reg.idx == EXTRA_REG_RSP_0) ?
> > +			x86_pmu.extra_msr_access[0] : true) &&
> > +		((hwc->extra_reg.idx == EXTRA_REG_RSP_1) ?
> > +			x86_pmu.extra_msr_access[1] : true))
> >  		wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
> >  	wrmsrl(hwc->config_base, (hwc->config | enable_mask) &
> > ~disable_mask);  }
> 
> > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
> > b/arch/x86/kernel/cpu/perf_event_intel.c
> > index adb02aa..3d18765 100644
> > --- a/arch/x86/kernel/cpu/perf_event_intel.c
> > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> 
> > +	/*
> > +	 * Access extra MSR may cause #GP under certain circumstances.
> > +	 * E.g. KVM doesn't support offcore event
> > +	 * Check all extra_regs here.
> > +	 */
> > +	if (x86_pmu.extra_regs) {
> > +		x86_pmu.extra_msr_access[0] =
> > +
> 	check_msr(x86_pmu.extra_regs[EXTRA_REG_RSP_0].msr);
> > +
> > +		/* Not all platforms have EXTRA_REG_RSP_1 */
> > +		if (x86_pmu.extra_regs[EXTRA_REG_RSP_1].idx ==
> EXTRA_REG_RSP_1)
> > +			x86_pmu.extra_msr_access[1] =
> > +
> 	check_msr(x86_pmu.extra_regs[EXTRA_REG_RSP_1].msr);
> > +		/*
> > +		 * If there is no EXTRA_REG_RSP_1 support,
> > +		 * just set the flag to be true.
> > +		 * So it is ignored at the runtime check.
> > +		 */
> > +		else
> > +			x86_pmu.extra_msr_access[1] = true;
> > +	}
> 
> This too is wrong in many ways; there's more than 2 extra_msrs on many
> systems.
> 
Right, there are four extra  reg types on Intel systems. Since my previous test only triggers the crash with RSP_0 and RSP_1, so I only handle these two msrs.
I will handle all the extra msrs then.

> And the place you check is abysmal, if we know at init time that we don't
> have those MSRs, WTF do you allow event creation that would use them,
> only to then misbehave?

Right, we can check it at all the possible creation places.
I think the most common place to check should be x86_pmu_extra_regs.
For RSP_0 and RSP_1, I also plan to do the check in intel_fixup_er, so extra_reg will not be updated.
For LBR select, lbr_sel_map will be cleared at runtime once check_msr failed.
Besides the three places, is there any place I missed?

Thanks,
Kan


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