Message-ID: <CAG374jBLq8YShOakBJtf2U47wuKGYNM7vSTn4PjzHsvjaYjmNQ@mail.gmail.com>
Date:	Wed, 9 Jul 2014 16:30:25 +0200
From:	Gabriel Fernandez <gabriel.fernandez@...aro.org>
To:	Lee Jones <lee.jones@...aro.org>
Cc:	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Kishon <kishon@...com>, "kernel@...inux.com" <kernel@...inux.com>
Subject: Re: [PATCH v3 1/5] phy: miphy365x: Add Device Tree bindings for the MiPHY365x

Hi Lee

One question below,

On 9 July 2014 13:41, Lee Jones <lee.jones@...aro.org> wrote:
> The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> devices. It has 2 ports which it can use for either; both SATA, both
> PCIe or one of each in any configuration.
>
> Cc: Kishon Vijay Abraham I <kishon@...com>
> Acked-by: Mark Rutland <mark.rutland@....com>
> Acked-by: Alexandre Torgue <alexandre.torgue@...com>
> Signed-off-by: Lee Jones <lee.jones@...aro.org>
> ---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 76 ++++++++++++++++++++++
>  1 file changed, 76 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> new file mode 100644
> index 0000000..7337ac2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> @@ -0,0 +1,76 @@
> +STMicroelectronics STi MIPHY365x PHY binding
> +============================================
> +
> +This binding describes a miphy device that is used to control PHY hardware
> +for SATA and PCIe.
> +
> +Required properties (controller (parent) node):
> +- compatible    : Should be "st,miphy365x-phy"
> +- st,syscfg     : Should be a phandle of the system configuration register group
> +                 which contain the SATA, PCIe mode setting bits
> +
> +Required nodes :  A sub-node is required for each channel the controller
> +                  provides. Address range information including the usual
> +                  'reg' and 'reg-names' properties are used inside these
> +                  nodes to describe the controller's topology. These nodes
> +                  are translated by the driver's .xlate() function.
> +
> +Required properties (port (child) node):
> +- #phy-cells   : Should be 1 (See second example)
> +                 Cell after port phandle is device type from:
> +                       - MIPHY_TYPE_SATA
> +                       - MIPHY_TYPE_PCI
> +- reg          : Address and length of register sets for each device in
> +                 "reg-names"
> +- reg-names     : The names of the register addresses corresponding to the
> +                 registers filled in "reg":
> +                       - sata:   For SATA devices
> +                       - pcie:   For PCIe devices
> +                       - syscfg: To specify the syscfg based config register
> +
> +Optional properties (port (child) node):
> +- st,sata-gen       :  Generation of locally attached SATA IP. Expected values
> +                       are {1,2,3). If not supplied generation 1 hardware will
> +                       be expected
> +- st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp)
> +- st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp)
> +
> +Example:
> +
> +       miphy365x_phy: miphy365x@...82000 {
> +               compatible      = "st,miphy365x-phy";
> +               st,syscfg       = <&syscfg_rear>;
> +               #address-cells  = <1>;
> +               #size-cells     = <1>;
> +               ranges;
> +
> +               phy_port0: port@...82000 {
> +                       reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
> +                       reg-names = "sata", "pcie", "syscfg";
> +                       #phy-cells = <1>;
> +                       st,sata-gen = <3>;
> +               };
> +
> +               phy_port1: port@...8a000 {
> +                       reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
> +                       reg-names = "sata", "pcie", "syscfg";
> +                       #phy-cells = <1>;
> +                       st,pcie-tx-pol-inv;
> +               };
> +       };
> +
> +Specifying phy control of devices
> +=================================
> +
> +Device nodes should specify the configuration required in their "phys"
> +property, containing a phandle to the phy port node and a device type.
> +
> +Example:
> +
> +#include <dt-bindings/phy/phy-miphy365x.h>
> +
> +       sata0: sata@...80000 {
> +               ...
> +               phys      = <&miphy365x_phy MIPHY_TYPE_SATA>;
> +               ...

In this example you select the type (SATA) but I don't understand how
do you select
the port (phy_port0 or phy_port1)

BR
Gabriel

> +       };
> --
> 1.8.3.2
>
>
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