linux-kernel - Re: WARNING: CPU: 2 PID: 1 at arch/x86/mm/ioremap.c:171 __ioremap

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Date:	Wed, 09 Jul 2014 20:41:17 +0200
From:	Fabio Coatti <fabio.coatti@...il.com>
To:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc:	linux-kernel@...r.kernel.org
Subject: Re: WARNING: CPU: 2 PID: 1 at arch/x86/mm/ioremap.c:171 __ioremap_caller+0x290/0x2fa()

In data lunedì 7 luglio 2014 13:47:47, Greg Kroah-Hartman ha scritto:
> On Mon, Jul 07, 2014 at 10:32:56PM +0200, Fabio Coatti wrote:
> > I'm seeing this message in latest kernels (this is from 3.15.4, but I have
> > same
> > message starting from 3.15.0, IIRC):
> So 3.14.0 didn't show this?
> 
> If so, can you run 'git bisect' between those two kernel versions to try
> to track down the issue?
> 
> thanks,
> 
> greg k-h
ok, I tried to bisect as suggested and got the commit reported below. However 
I'm not really sure to have got the right one, as one kernel refused to 
compile during the last steps. However I post here the result, maybe they can 
be useful.
Tomorrow I can retry the whole process again starting from different commits.


b9e1ab6d4c0582cad97699285a6b3cf992251b00 is the first bad commit
commit b9e1ab6d4c0582cad97699285a6b3cf992251b00
Author: Stephane Eranian <eranian@...gle.com>
Date:   Tue Feb 11 16:20:12 2014 +0100

    perf/x86/uncore: add SNB/IVB/HSW client uncore memory controller support
    
    This patch adds a new uncore PMU for Intel SNB/IVB/HSW client
    CPUs. It adds the Integrated Memory Controller (IMC) PMU. This
    new PMU provides a set of events to measure memory bandwidth utilization.
    
    The IMC on those processor is PCI-space based. This patch
    exposes a new uncore PMU on those processor: uncore_imc
    
    Two new events are defined:
      - name: data_reads
      - code: 0x1
      - unit: 64 bytes
      - number of full cacheline read requests to the IMC
    
      - name: data_writes
      - code: 0x2
      - unit: 64 bytes
      - number of full cacheline write requests to the IMC
    
    Documentation available at:
    http://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel
    
    Cc: mingo@...e.hu
    Cc: acme@...hat.com
    Cc: ak@...ux.intel.com
    Cc: zheng.z.yan@...el.com
    Cc: peterz@...radead.org
    Signed-off-by: Stephane Eranian <eranian@...gle.com>
    Signed-off-by: Peter Zijlstra <peterz@...radead.org>                                                                                                                                        
    Link: http://lkml.kernel.org/r/1392132015-14521-7-git-send-email-eranian@google.com                                                                                                         
    Signed-off-by: Thomas Gleixner <tglx@...utronix.de>                                                                                                                                         
                                                                                                                                                                                                
:040000 040000 2d628022cbc4b8969a2ec311082053510cf6eed5 
79b2a1cc3ed29e4820a5ae4221b4cf603c138887 M      arch   


-- 
Fabio
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