lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Thu, 10 Jul 2014 10:00:44 +0200
From:	Tomeu Vizoso <>
To:	Tomasz Figa <>,
	Stephen Warren <>,
	Thierry Reding <>,
	Mike Turquette <>,,,,
CC:	Javier Martinez Canillas <>
Subject: Re: [RFC v2 0/5] Per-user clock constraints

On 07/09/2014 10:16 PM, Tomasz Figa wrote:
> Hi Tomeu,
> On 03.07.2014 16:38, Tomeu Vizoso wrote:
>> Hello,
>> here is another round for commenting, not very different from the first one.
>> Something I forgot to mention before is that the function rename was performed
>> by the scripts in:
>> As before, I have only checked that drivers/clk/ builds with allyesconfig, and
>> that a kernel can be built for tegra_defconfig.
> This is quite an interesting series. I have reviewed two of five patches
> and have plans to look at remaining ones, however here are few general
> issues I'd like to raise:
> - somehow I don't see patch 2/5 on LAKML. Too big?

Yes, I'm not sure what I can do about that, but it's only automated 
function renaming. I'm going to send v3 in a bit and will CC you.

> - I see the series changing particular clock drivers. A good practice
> would be to Cc respective driver maintainers to take a look at those
> changes.

Now that I'm more confident about this approach, for the next version 
I'm going to CC them as well.

> - please make sure that all the patches don't have checkpatch errors or
> significant warnings.


> Will try (myself or by asking someone else) to do some testing on
> Samsung platforms.

That will be great, thanks. One scenario I'm looking forward to test 
this with is low system load while the display is being updated often at 
a high resolution.

I would expect to see that the Exynos5 devfreq driver sets a relatively 
low floor frequency, and the DC driver overrides that by setting a 
higher floor, based on the calculated bandwidth that will be required to 
move pixels around.



> Best regards,
> Tomasz

To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

Powered by blists - more mailing lists