linux-kernel - [PATCH 65/83] hsa/radeon: fixing a bug to support 32b processes

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Message-Id: <1405029279-6894-37-git-send-email-oded.gabbay@amd.com>
Date:	Fri, 11 Jul 2014 00:54:21 +0300
From:	Oded Gabbay <oded.gabbay@...il.com>
To:	David Airlie <airlied@...ux.ie>,
	Alex Deucher <alexander.deucher@....com>,
	Jerome Glisse <j.glisse@...il.com>
Cc:	linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
	John Bridgman <John.Bridgman@....com>,
	Andrew Lewycky <Andrew.Lewycky@....com>,
	Joerg Roedel <joro@...tes.org>, Ben Goz <ben.goz@....com>,
	Oded Gabbay <oded.gabbay@....com>
Subject: [PATCH 65/83] hsa/radeon: fixing a bug to support 32b processes

From: Ben Goz <ben.goz@....com>

This commit is a bug fix for 32b hsa processes support

Signed-off-by: Ben Goz <ben.goz@....com>
Signed-off-by: Oded Gabbay <oded.gabbay@....com>
---
 drivers/gpu/hsa/radeon/cik_regs.h                 | 1 +
 drivers/gpu/hsa/radeon/kfd_device_queue_manager.c | 8 +++++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/hsa/radeon/cik_regs.h b/drivers/gpu/hsa/radeon/cik_regs.h
index fa5ec01..a6404e3 100644
--- a/drivers/gpu/hsa/radeon/cik_regs.h
+++ b/drivers/gpu/hsa/radeon/cik_regs.h
@@ -45,6 +45,7 @@
 /* if PTR32, this is the upper limit of GPUVM */
 #define	SH_MEM_CONFIG					0x8C34
 #define	PTR32						(1 << 0)
+#define PRIVATE_ATC					(1 << 1)
 #define	ALIGNMENT_MODE(x)				((x) << 2)
 #define	SH_MEM_ALIGNMENT_MODE_DWORD			0
 #define	SH_MEM_ALIGNMENT_MODE_DWORD_STRICT		1
diff --git a/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c b/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c
index 01573b1..3e1def1 100644
--- a/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c
+++ b/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c
@@ -90,15 +90,17 @@ static void init_process_memory(struct device_queue_manager *dqm, struct qcm_pro
 	if (qpd->pqm->process->is_32bit_user_mode) {
 		temp = get_sh_mem_bases_32(qpd->pqm->process, dqm->dev);
 		qpd->sh_mem_bases = SHARED_BASE(temp);
+		qpd->sh_mem_config = PTR32;
 	} else {
 		temp = get_sh_mem_bases_nybble_64(qpd->pqm->process, dqm->dev);
 		qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
+		qpd->sh_mem_config = 0;
 	}
 
-	qpd->sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+	qpd->sh_mem_config |= ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 	qpd->sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
 	qpd->sh_mem_ape1_limit = 0;
-	qpd->sh_mem_ape1_base = 1;
+	qpd->sh_mem_ape1_base = 0;
 
 	pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
 		qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
@@ -854,7 +856,7 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm)
 	}
 
 	if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
-				return 0;
+		return 0;
 
 	mutex_lock(&dqm->lock);
 	if (dqm->active_runlist) {
-- 
1.9.1

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