lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Mon, 14 Jul 2014 09:48:53 +0100
From:	Srinivas Kandagatla <>
To:	Kishon Vijay Abraham I <>
Cc:	Grant Likely <>,
	Rob Herring <>,,,,
	Srinivas Kandagatla <>
Subject: [PATCH v3 2/2] phy: qcom: Update APQ8064 PHY device tree bindings

Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the APQ8064 family of SoCs

Signed-off-by: Srinivas Kandagatla <>
 Documentation/devicetree/bindings/phy/qcom-phy.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt b/Documentation/devicetree/bindings/phy/qcom-phy.txt
index 76bfbd0..6bff1e0 100644
--- a/Documentation/devicetree/bindings/phy/qcom-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
@@ -1,4 +1,4 @@
-Qualcomm IPQ806x SATA PHY Controller
+Qualcomm IPQ806x/APQ8064 SATA PHY Controller
 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
@@ -6,6 +6,7 @@ Each SATA PHY controller should have its own node.
 Required properties:
 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
+	     or "qcom,apq8064-sata-phy".
 - reg: offset and length of the SATA PHY register set;
 - #phy-cells: must be zero
 - clocks: must be exactly one entry

To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

Powered by blists - more mailing lists