Message-ID: <20140714102954.GD9870@ulmo>
Date:	Mon, 14 Jul 2014 12:29:56 +0200
From:	Thierry Reding <thierry.reding@...il.com>
To:	Mikko Perttunen <mperttunen@...dia.com>
Cc:	Mikko Perttunen <mikko.perttunen@...si.fi>,
	Peter De Schrijver <pdeschrijver@...dia.com>,
	Prashant Gaikwad <pgaikwad@...dia.com>,
	"mturquette@...aro.org" <mturquette@...aro.org>,
	"swarren@...dotorg.org" <swarren@...dotorg.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>
Subject: Re: [PATCH 5/8] of: Add Tegra124 EMC bindings

On Mon, Jul 14, 2014 at 12:57:26PM +0300, Mikko Perttunen wrote:
> On 14/07/14 12:31, Thierry Reding wrote:
> >* PGP Signed by an unknown key
> >
> >On Mon, Jul 14, 2014 at 12:06:32PM +0300, Mikko Perttunen wrote:
> >>On 14/07/14 11:15, Thierry Reding wrote:
> >>>>Old Signed by an unknown key
> >>>
> >>>On Mon, Jul 14, 2014 at 10:55:51AM +0300, Mikko Perttunen wrote:
> >>>>On 11/07/14 19:01, Mikko Perttunen wrote:
> >>>>>On 07/11/2014 05:51 PM, Thierry Reding wrote:
> >>>>>>On Fri, Jul 11, 2014 at 05:18:30PM +0300, Mikko Perttunen wrote:
> >>>>>>>...
> >>>>>>...
> >>>>>
> >>>>>In this case, all the registers that will be written are such that the
> >>>>>MC driver will never need to write them. They are shadowed registers,
> >>>>>meaning that all writes are stored and are only effective starting from
> >>>>>the next time the EMC rate change state machine is activated, so writing
> >>>>>them from anywhere except than the EMC driver would be pointless.
> >>>>>
> >>>>>I can find two users of these registers in downstream:
> >>>>>1) mc.c saves and loads them on suspend/restore (I don't know why, that
> >>>>>shouldn't do anything. They will be overridden anyway during the next
> >>>>>EMC rate change).
> >>>>>2) tegra12x_la.c reads MC_EMEM_ARB_MISC0 during a core_initcall to
> >>>>>calculate a value which it then writes to a register that is also
> >>>>>shadowed and that is part of downstream burst registers so that doesn't
> >>>>>do anything either.
> >>>>>
> >>>>>The reason I implemented two ways to specify the MC register area was
> >>>>>that this could be merged before an MC driver and retain
> >>>>>backwards-compatibility after the MC driver arrives.
> >>>>>
> >>>>>If this is not acceptable, we can certainly wait for the MC driver to be
> >>>>>merged first. (Although with the general rate of things, I hope I won't
> >>>>>be back at school at that point..) I assume that this is blocked on the
> >>>>>IOMMU bindings discussion? In that case, there are several options: the
> >>>>>MC driver could have its own tables for each EMC rate or we could just
> >>>>>make the EMC tables global (i.e. not under the EMC node). In any case,
> >>>>>the MC driver would need to implement a function that would just write
> >>>>>these values but be guaranteed to not do anything else, since that could
> >>>>>cause nasty things during the EMC rate change sequence.
> >>>>
> >>>>Having taken another look at the code, I don't think the MC driver could do
> >>>>anything that bad. There are also two other places where the EMC driver
> >>>>needs to read MC registers: Inside the sequence, it reads a register but
> >>>>discards its contents. According to comments, this acts as a memory barrier,
> >>>>probably for the preceding step that writes into MC memory. If the register
> >>>>writes are moved to the MC driver, it could also handle that. In another
> >>>>place it reads the number of RAM modules from a MC register. The MC driver
> >>>>could export this as another function.
> >>>
> >>>Exporting this functionality from the MC driver is the right thing to do
> >>>in my opinion.
> >>
> >>Ok, let's do that then. Do you think I could make a bare-bones MC driver to
> >>support the EMC driver before your MC driver with IOMMU/LA is ready? Can the
> >>MC device tree node be stabilized yet? Of course, if things go well, that
> >>concern might turn out to be unnecessary.
> >
> >Well, at this point this isn't 3.17 material anyway, so there's no need
> >to rush things.
> 
> Very true.
> 
> >I'd prefer to take a patch on top of my proposed MC
> >driver patch in anticipation of merging that for 3.18. But if it turns
> >out that for whatever reason we can't do that, having a separate patch
> >makes it easy to extract the changes into a bare-bones driver.
> 
> Yes, this sounds sensible. I'll make such a patch. I suppose having another
> timings table in the MC node with just the rate and mc-burst-data would
> separate the concerns best. It occurs to me that we could also write the
> regs in the pre-rate change notifier, but this would turn the dependency
> around and would mean that the regs are not written when entering backup
> rates. The latter shouldn't be a problem but the reversed dependency would,
> so I guess a custom function is the way to go, and we need to add at least
> one anyway.

It sounds like maybe moving enough code and data into the MC driver to
handle frequency changes would be a good move. From the above it sounds
like all the MC driver needs to know is that a frequency change is about
to happen and what the new frequency is.

In addition to exposing things like number of DRAM banks, etc.

> The downstream kernel also overwrites most LA registers during EMC rate
> change without regard for the driver-set values, and we might have to read
> those values from the device tree too. Upstream can do this in rate change
> notifiers if needed. I'll look into this a bit more.

As I understand it, the latency allowance should be specified in terms
of the maximum amount of time that requests are delayed, so that the
proper values for the LA registers can be recomputed on an EMC rate
change.

Thierry

Content of type "application/pgp-signature" skipped

Powered by blists - more mailing lists