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Date:	Mon, 14 Jul 2014 15:33:25 -0400 (EDT)
From:	Vince Weaver <>
cc:	Peter Zijlstra <>,
	Ingo Molnar <>,
	Arnaldo Carvalho de Melo <>,
	Andi Kleen <>,
	Dave Hansen <>,
	Stephane Eranian <>
Subject: [patch] perf: use proper dTLB-load-misses event on Ivybridge

This was discussed back in February
But I never saw a patch come out of it.

On Ivybridge we share the Sandybridge cache event tables, but the
dTLB-load-miss event is not compatible.  Patch it up after

Signed-off-by: Vince Weaver <>

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index adb02aa..f5784f0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2465,6 +2465,9 @@ __init int intel_pmu_init(void)
 	case 62: /* IvyBridge EP */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
+		/* dTLB-load-misses on IVB is different than SNB */
+		hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
 		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
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