linux-kernel - Re: [PATCH RFC] percpu: add data dependency barrier in percpu accessors and operations

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Date:	Tue, 15 Jul 2014 10:06:01 -0500 (CDT)
From:	Christoph Lameter <cl@...two.org>
To:	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
cc:	Rusty Russell <rusty@...tcorp.com.au>, Tejun Heo <tj@...nel.org>,
	David Howells <dhowells@...hat.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Oleg Nesterov <oleg@...hat.com>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC] percpu: add data dependency barrier in percpu
 accessors and operations

On Tue, 15 Jul 2014, Paul E. McKenney wrote:

> On Tue, Jul 15, 2014 at 09:06:00AM -0500, Christoph Lameter wrote:
> > On Tue, 15 Jul 2014, Paul E. McKenney wrote:
> >
> > > If I understand your initialization procedure correctly, you need at least
> > > an smp_wmb() on the update side and at least an smp_read_barrier_depends()
> > > on the read side.
> >
> > A barrier for data that is not in the cache of the read side? That has
> > not been accessed yet (well there could have been a free_percpu before but
> > if so then the cache line was evicted by the initialization code).
>
> http://www.openvms.compaq.com/wizard/wiz_2637.html

Not sure what the intend of this link is?

> Besides which, if you don't have barriers on the initialization side,
> then both the CPU and the compiler are free to update the pointer before
> completing the initialization, which can leave old stuff still in other
> CPUs' caches for long enough to break you.

The cachelines will be evicted from the other processors at
initialization. alloc_percpu *itself* zeroes all data on each percpu areas
before returning the offset to the percpu data structure. See
pcpu_populate_chunk(). At that point *all* other processors have those
cachelines no longer in their caches. The initialization done with values
specific to the subsystem is not that important.

The return value of the function is only available after
pcpu_populate_chunk() returns.

Access to those cachelines is possible only after the other processors
have obtained the offset that was stored in some data struture. That
usually involves additional synchronization which implies barriers
anyways.

I do not think there is anything here.
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