linux-kernel - [PATCH 51/94] ARM: dts: Update the parent for Audss clocks in Exynos5420

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Message-Id: <1405443709-15288-51-git-send-email-asadi.samuel@gmail.com>
Date:	Tue, 15 Jul 2014 20:01:06 +0300
From:	Sam Asadi <asadi.samuel@...il.com>
To:	gregkh@...uxfoundation.org
Cc:	devel@...verdev.osuosl.org, linux-kernel@...r.kernel.org,
	Tushar Behera <tushar.b@...sung.com>,
	Shaik Ameer Basha <shaik.ameer@...sung.com>,
	Kukjin Kim <kgene.kim@...sung.com>,
	sam-the-6 <asadi.samuel@...il.com>
Subject: [PATCH 51/94] ARM: dts: Update the parent for Audss clocks in Exynos5420

From: Tushar Behera <tushar.b@...sung.com>

Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.

The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.

Signed-off-by: Tushar Behera <tushar.b@...sung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@...sung.com>
Reported-by: Kevin Hilman <khilman@...aro.org>
Tested-by: Javier Martinez Canillas <javier.martinez@...labora.co.uk>
Tested-by: Doug Anderson <dianders@...omium.org>
Signed-off-by: Kukjin Kim <kgene.kim@...sung.com>
Signed-off-by: sam-the-6 <asadi.samuel@...il.com>
---
 arch/arm/boot/dts/exynos5420.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..79e9119 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -167,7 +167,7 @@
 		compatible = "samsung,exynos5420-audss-clock";
 		reg = <0x03810000 0x0C>;
 		#clock-cells = <1>;
-		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 			 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 	};
-- 
1.7.10.4

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