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Message-ID: <20140717094101.GD21153@arm.com> Date: Thu, 17 Jul 2014 10:41:02 +0100 From: Will Deacon <will.deacon@....com> To: Zi Shen Lim <zlim.lnx@...il.com> Cc: Catalin Marinas <Catalin.Marinas@....com>, Jiang Liu <liuj97@...il.com>, AKASHI Takahiro <takahiro.akashi@...aro.org>, "David S. Miller" <davem@...emloft.net>, Daniel Borkmann <dborkman@...hat.com>, Alexei Starovoitov <ast@...mgrid.com>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "netdev@...r.kernel.org" <netdev@...r.kernel.org> Subject: Re: [PATCH RFCv3 08/14] arm64: introduce aarch64_insn_gen_movewide() On Wed, Jul 16, 2014 at 11:04:22PM +0100, Zi Shen Lim wrote: > On Wed, Jul 16, 2014 at 05:17:15PM +0100, Will Deacon wrote: > > On Tue, Jul 15, 2014 at 07:25:06AM +0100, Zi Shen Lim wrote: > > > Introduce function to generate move wide (immediate) instructions. > > > > [...] > > > > > +u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst, > > > + int imm, int shift, > > > + enum aarch64_insn_variant variant, > > > + enum aarch64_insn_movewide_type type) > > > +{ > > > + u32 insn; > > > + > > > + switch (type) { > > > + case AARCH64_INSN_MOVEWIDE_ZERO: > > > + insn = aarch64_insn_get_movz_value(); > > > + break; > > > + case AARCH64_INSN_MOVEWIDE_KEEP: > > > + insn = aarch64_insn_get_movk_value(); > > > + break; > > > + case AARCH64_INSN_MOVEWIDE_INVERSE: > > > + insn = aarch64_insn_get_movn_value(); > > > + break; > > > + default: > > > + BUG_ON(1); > > > + } > > > + > > > + BUG_ON(imm < 0 || imm > 65535); > > > > Do this check with masking instead? > > Ok, if you prefer, I can change it to: > > BUG_ON(imm & ~GENMASK(15, 0)); Sure, that or use a named constant for the upper-bound (SZ_64K - 1). > > > + switch (variant) { > > > + case AARCH64_INSN_VARIANT_32BIT: > > > + BUG_ON(shift != 0 && shift != 16); > > > + break; > > > + case AARCH64_INSN_VARIANT_64BIT: > > > + insn |= BIT(31); > > > + BUG_ON(shift != 0 && shift != 16 && shift != 32 && > > > + shift != 48); > > > > Would be neater as a nested switch, perhaps? If you reorder the > > outer-switch, you could probably fall-through too and combine the shift > > checks. > > Not sure I picture what you had in mind... I couldn't come up with a > neater version with the properties you described. > > The alternative I had was using masks instead of integer values, but > one could argue that while neater, it could also be harder to read: > > switch (variant) { > case AARCH64_INSN_VARIANT_32BIT: > BUG_ON(shift & ~BIT(4)); > break; > case AARCH64_INSN_VARIANT_64BIT: > insn |= BIT(31); > BUG_ON(shift & ~GENMASK(5, 4)); > ... I was thinking of using nested switches, but that doesn't fall out like I hoped. How about: switch (variant) { case AARCH64_INSN_VARIANT_64BIT: BUG_ON(shift != 32 && shift != 48); case AARCH64_INSN_VARIANT_32BIT: BUG_ON(shift != 0 && shift != 16); }; ? Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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