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Message-Id: <3d84500701239b649de3a1887dcac6356e1516ad.1405685481.git.jslaby@suse.cz>
Date: Fri, 18 Jul 2014 14:12:36 +0200
From: Jiri Slaby <jslaby@...e.cz>
To: stable@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
Mike Turquette <mturquette@...aro.org>,
Jiri Slaby <jslaby@...e.cz>
Subject: [PATCH 3.12 151/170] clk: spear3xx: Use proper control register offset
From: Thomas Gleixner <tglx@...utronix.de>
3.12-stable review patch. If anyone has any objections, please let me know.
===============
commit 15ebb05248d025534773c9ef64915bd888f04e4b upstream.
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Acked-by: Viresh Kumar <viresh.kumar@...aro.org>
Signed-off-by: Mike Turquette <mturquette@...aro.org>
Signed-off-by: Jiri Slaby <jslaby@...e.cz>
---
drivers/clk/spear/spear3xx_clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index c2d204315546..125eba86c844 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { }
/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320
-#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
+#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010)
#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
#define SPEAR320_UARTX_PCLK_MASK 0x1
--
2.0.0
--
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