linux-kernel - Re: STI architectural question (and lretq -- I'm not even kidding)

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Tue, 22 Jul 2014 18:03:35 -0700
From:	Linus Torvalds <torvalds@...ux-foundation.org>
To:	Andy Lutomirski <luto@...capital.net>
Cc:	"H. Peter Anvin" <hpa@...ux.intel.com>,
	Borislav Petkov <bp@...en8.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	X86 ML <x86@...nel.org>
Subject: Re: STI architectural question (and lretq -- I'm not even kidding)

On Tue, Jul 22, 2014 at 5:10 PM, Andy Lutomirski <luto@...capital.net> wrote:
>
> But here's the problem: what happens if an NMI or MCE happens between
> the sti and the lretq?  I think an MCE just might be okay -- it's not
> really recoverable anyway.  (Except for the absurd MCE broadcast crap,
> which may cause this to be a problem.)  But what about an NMI between
> sti and lretq?

Sadly, it's not architected.

The "mov ss" and "pop ss" do indeed suppress even NMI. And that *has*
to be true, because in legacy real mode - where there is no protection
domain change, and the "lss" instruction didn't originally exist - the
"pop/mov ss" and "mov sp" instruction sequence had to be entirely
atomic. And this is even very officially documented. From the intel
system manual:

    "A POP SS instruction inhibits all interrupts, including the NMI
interrupt, until after execution of the next instruction. This action
allows sequential execution of POP SS and MOV ESP, EBP instructions
without the danger of having an invalid stack during an interrupt.
However, use of the LSS instruction is the preferred method of loading
the SS and ESP registers"

However, while "sti" has conceptually the same one-instruction
interrupt window disable as mov/pop ss, it looks like Intel broke it
for NMI. The documentation only talks about "external, maskable
interrupts", and while I suspect *many* micro-architectures also end
up disabling NMI for the next instruction, there are many reasons to
think not all do.

See for example

    http://www.sandpile.org/x86/inter.htm

and note #5 under external interrupt suppression.

Now, sandpile is pretty old, but Christian Ludloff used to get things
like that right.

So I'm afraid that "sti; lret" is not guaranteed to be architecturally
NMI-safe. But it *might* be safe on certain micro-architectures, and
maybe somebody inside Intel or AMD can give us a hint about when it is
safe and when it isn't.

                Linus
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/