linux-kernel - Re: [PATCH v2] mm/highmem: make kmap cache coloring aware

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20140724152133.bd4556f632b9cbb506b168cf@linux-foundation.org>
Date:	Thu, 24 Jul 2014 15:21:33 -0700
From:	Andrew Morton <akpm@...ux-foundation.org>
To:	Max Filippov <jcmvbkbc@...il.com>
Cc:	"linux-mm@...ck.org" <linux-mm@...ck.org>,
	Linux-Arch <linux-arch@...r.kernel.org>,
	"Linux/MIPS Mailing List" <linux-mips@...ux-mips.org>,
	"linux-xtensa@...ux-xtensa.org" <linux-xtensa@...ux-xtensa.org>,
	LKML <linux-kernel@...r.kernel.org>,
	Leonid Yegoshin <Leonid.Yegoshin@...tec.com>,
	Chris Zankel <chris@...kel.net>,
	Marc Gauthier <marc@...ence.com>
Subject: Re: [PATCH v2] mm/highmem: make kmap cache coloring aware

On Thu, 24 Jul 2014 04:38:01 +0400 Max Filippov <jcmvbkbc@...il.com> wrote:

> On Thu, Jul 24, 2014 at 1:17 AM, Andrew Morton
> <akpm@...ux-foundation.org> wrote:
> > Fifthly, it would be very useful to publish the performance testing
> > results for at least one architecture so that we can determine the
> > patchset's desirability.  And perhaps to motivate other architectures
> > to implement this.
> 
> What sort of performance numbers would be relevant?
> For xtensa this patch enables highmem use for cores with aliasing cache,
> that is access to a gigabyte of memory (typical on KC705 FPGA board) vs.
> only 128MBytes of low memory, which is highly desirable. But performance
> comparison of these two configurations seems to make little sense.
> OTOH performance comparison of highmem variants with and without
> cache aliasing would show the quality of our cache flushing code.

I'd assumed the patch was making cache coloring available as a
performance tweak.  But you appear to be saying that the (high) memory
is simply unavailable for such cores without this change.  I think.

Please ensure that v3's changelog explains the full reason for the
patch.  Assume you're talking to all-the-worlds-an-x86 dummies, OK?

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/