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Message-ID: <ddb38ce5-9e31-4c94-967c-7784c7fba75c@BN1BFFO11FD028.protection.gbl>
Date: Thu, 24 Jul 2014 16:18:29 -0700
From: Sören Brinkmann <soren.brinkmann@...inx.com>
To: Andreas Färber <afaerber@...e.de>
CC: Michal Simek <michal.simek@...inx.com>,
Andreas Olofsson <andreas@...pteva.com>,
Matteo Vit <matteo.vit@...rwaredesign.com>,
Sean Rickerd <srickerd@...e.com>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Russell King <linux@....linux.org.uk>
Subject: Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella
On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> Prepare SPI0 and SPI1 while at it.
>
> Signed-off-by: Andreas Färber <afaerber@...e.de>
> ---
> v2: New
>
> arch/arm/boot/dts/zynq-7000.dtsi | 37 +++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/zynq-parallella.dts | 4 ++++
> 2 files changed, 41 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index 8fd826a..eed3df0 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -122,6 +122,30 @@
> interrupts = <0 50 4>;
> };
>
> + spi0: spi@...06000 {
> + compatible = "xlnx,zynq-spi-r1p6";
> + reg = <0xe0006000 0x1000>;
> + status = "disabled";
> + interrupt-parent = <&intc>;
> + interrupts = <0 26 4>;
> + clocks = <&clkc 25>, <&clkc 34>;
> + clock-names = "ref_clk", "pclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@...07000 {
> + compatible = "xlnx,zynq-spi-r1p6";
> + reg = <0xe0007000 0x1000>;
> + status = "disabled";
> + interrupt-parent = <&intc>;
> + interrupts = <0 49 4>;
> + clocks = <&clkc 26>, <&clkc 35>;
> + clock-names = "ref_clk", "pclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
Until here things look good.
> gem0: ethernet@...0b000 {
> compatible = "cdns,gem";
> reg = <0xe000b000 0x4000>;
> @@ -140,6 +164,19 @@
> clock-names = "pclk", "hclk", "tx_clk";
> };
>
> + qspi: qspi@...0d000 {
> + compatible = "xlnx,zynq-spi-r1p6";
> + reg = <0xe000d000 0x1000>;
> + status = "disabled";
> + interrupt-parent = <&intc>;
> + interrupts = <0 19 4>;
> + clocks = <&clkc 10>, <&clkc 43>;
> + clock-names = "ref_clk", "pclk";
> + num-cs = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
I'm not sure what the status of this driver is. I think QSPI is still
under review on the mailing lists and I don't think we should add this
yet.
Sören
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