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Date:	Mon, 28 Jul 2014 16:15:50 -0500
From:	Felipe Balbi <balbi@...com>
To:	Tony Lindgren <tony@...mide.com>
CC:	Linux OMAP Mailing List <linux-omap@...r.kernel.org>,
	Linux ARM Kernel Mailing List 
	<linux-arm-kernel@...ts.infradead.org>, <bcousson@...libre.com>,
	<linux@....linux.org.uk>, <khilman@...prootsystems.com>,
	<tglx@...utronix.de>, <jason@...edaemon.net>,
	<devicetree@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Felipe Balbi <balbi@...com>
Subject: [PATCH 02/35] arm: omap: irq: define INTC_ILR0 register

this is currently used as a hardcoded 0x100
offset.

Signed-off-by: Felipe Balbi <balbi@...com>
---
 arch/arm/mach-omap2/irq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 7b2cf9a..96073a2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -41,6 +41,7 @@
 #define INTC_MIR_CLEAR0		0x0088
 #define INTC_MIR_SET0		0x008c
 #define INTC_PENDING_IRQ0	0x0098
+#define INTC_ILR0		0x0100
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG	32
 
-- 
2.0.1.563.g66f467c

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