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Message-ID: <53D8886A.5020600@ti.com>
Date:	Wed, 30 Jul 2014 08:53:46 +0300
From:	Peter Ujfalusi <peter.ujfalusi@...com>
To:	Mike Turquette <mturquette@...aro.org>,
	Tero Kristo <t-kristo@...com>
CC:	Tony Lindgren <tony@...mide.com>,
	Linux OMAP Mailing List <linux-omap@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: ti: clk-7xx: Correct ABE DPLL configuration

On 07/29/2014 07:12 PM, Mike Turquette wrote:
>> Oh yea, seems this got lost into the myriad of branches I have. I can push
>> this on top of my for-v3.17/ti-clk-drv if you like.
> 
> That is the easiest thing for me. I think that Peter wanted to take
> this as a fix for 3.16 though. Peter is that correct?

Yes, it would have been better to have it in 3.16 along with the DRA7 ATL
clock driver. W/O this patch the ATL will not going to be usable since the ABE
DPLL is set too high to be usable for it's purpose.

-- 
Péter
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