linux-kernel - Re: [PATCH v7 4/5] PCI: add PCI controller for keystone PCIe h/w

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Wed, 30 Jul 2014 15:34:44 -0400
From:	Murali Karicheri <m-karicheri2@...com>
To:	Jason Gunthorpe <jgunthorpe@...idianresearch.com>
CC:	Bjorn Helgaas <bhelgaas@...gle.com>,
	Richard Zhu <r65037@...escale.com>,
	Marek Vasut <marex@...x.de>,
	Randy Dunlap <rdunlap@...radead.org>,
	Russell King <linux@....linux.org.uk>,
	Pawel Moll <pawel.moll@....com>, Arnd Bergmann <arnd@...db.de>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	<linux-pci@...r.kernel.org>, Jingoo Han <jg1.han@...sung.com>,
	<linux-kernel@...r.kernel.org>,
	Kishon Vijay Abraham I <kishon@...com>,
	Rob Herring <robh+dt@...nel.org>,
	Santosh Shilimkar <santosh.shilimkar@...com>,
	Kumar Gala <galak@...eaurora.org>,
	Grant Likely <grant.likely@...aro.org>,
	Mark Rutland <mark.rutland@....com>,
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v7 4/5] PCI: add PCI controller for keystone PCIe h/w

On 07/23/2014 01:42 PM, Jason Gunthorpe wrote:
> On Tue, Jul 22, 2014 at 05:52:00PM -0600, Bjorn Helgaas wrote:
>> If there is a hardware defect, a PCI quirk is a reasonable way to work
>> around it, since that's the main purpose of quirks.  fixup_mpss_256()
>> is an example of something that sounds superficially similar.
>
> It was my suggestion to engage the PCI-E tuning code. By my
> understanding the HW bug is that read response segmentation at the
> host bridge does not work - so all read requests from any downstream
> device must have responses that fit within a single packet.
>

In the case of Keystone PCI, when I set the MRSS to 256 in the EP, PCI 
controller is able to function properly. Keystone spec says.

• Maximum outbound payload size of 128 bytes
• Maximum inbound payload size of 256 bytes
• Maximum remote read request size of 256 bytes

I am interpreting the "Maximum remote read request size" to indicate it 
can's handle if it exceeds the limit. It has an outbound payload size of 
128 bytes. So in this case a read request would results in 2 completion 
packets. So it seems to be able to segment up to maximum 256 bytes of 
read request. Where do I find the requirement in PCI spec that "read 
response segmentation at the host bridge does not work" ?

> This is completely against how the spec envisions things working,
> segmentation is a mandatory function. As you point out there is no
> parameter bounding the maximum read request size that a completer will
> accept.
>
> So, the only fix is that every downstream device must always have a
> MRSS set to less than the MPS of the host bridge.

Why this can't be the default behavior in the PCI core? Any cons?

Murali
>
> Which means the tuning code must be involved somehow, as that code
> controls the MRSS of unrelated devices...
>
> Regards,
> Jason

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/