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Date: Thu, 31 Jul 2014 15:37:01 +0200
From: Humberto Naves <hsnaves@...il.com>
To: Tomasz Figa <tomasz.figa@...il.com>
Cc: linux-samsung-soc <linux-samsung-soc@...r.kernel.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, devicetree@...r.kernel.org,
Kukjin Kim <kgene.kim@...sung.com>,
Tomasz Figa <t.figa@...sung.com>,
Thomas Abraham <ta.omasab@...il.com>,
Andreas Farber <afaerber@...e.de>,
Randy Dunlap <rdunlap@...radead.org>,
Ian Campbell <ijc+devicetree@...lion.org.uk>
Subject: Re: [PATCHv2 5/5] clk: samsung: exynos5410: Added clocks DPLL, EPLL,
IPLL, and VPLL
Hi Tomasz,
I remember checking these rates on my calculator. You might notice the
odd frequency of 45158401Hz (no pun intended) in the EPLL clock. This
particular clock frequency was giving me a big headache in a previous
project, since it was wrongly listed as 45158400. At first it seems
innocuous, but whenever I would ask for one of the child clocks to
change the rate, the driver would miscalculate the correct frequencies
and errors would propagate up and down the clock tree.
Anyway, I would double check these tables. And if you want, I can
write a separate patch for the rate table validation. I presume that
you would like to add a new field, such as default_base_freq, to the
structure samsung_pll_clock, and if that field is non-zero, you
perform the validation of the table in _samsung_clk_register_pll?
Best,
Humberto
On Thu, Jul 31, 2014 at 3:07 PM, Tomasz Figa <tomasz.figa@...il.com> wrote:
> Hi Humberto,
>
> You can find my comments inline.
>
> On 31.07.2014 13:22, Humberto Silva Naves wrote:
>> Added the remaining PLL clocks, and also added the configuration
>> tables with the PLL coefficients for the supported frequencies.
>> These frequency tables are only installed when a 24MHz clock is
>> supplied as the input clock source. To reflect these changes, new
>> constants were added to the dt-bindings file.
>
> [snip]
>
>> +static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
>> + /* sorted in descending order */
>> + /* PLL_35XX_RATE(rate, m, p, s) */
>> + PLL_35XX_RATE(2100000000, 175, 2, 0),
>> + PLL_35XX_RATE(2000000000, 250, 3, 0),
>> + PLL_35XX_RATE(1900000000, 475, 6, 0),
>> + PLL_35XX_RATE(1800000000, 225, 3, 0),
>> + PLL_35XX_RATE(1700000000, 425, 6, 0),
>> + PLL_35XX_RATE(1600000000, 200, 3, 0),
>> + PLL_35XX_RATE(1500000000, 250, 4, 0),
>> + PLL_35XX_RATE(1400000000, 175, 3, 0),
>> + PLL_35XX_RATE(1300000000, 325, 6, 0),
>> + PLL_35XX_RATE(1200000000, 100, 2, 0),
>> + PLL_35XX_RATE(1100000000, 275, 3, 1),
>> + PLL_35XX_RATE(1000000000, 250, 3, 1),
>> + PLL_35XX_RATE(900000000, 150, 2, 1),
>> + PLL_35XX_RATE(800000000, 200, 3, 1),
>> + PLL_35XX_RATE(700000000, 175, 3, 1),
>> + PLL_35XX_RATE(600000000, 100, 2, 1),
>> + PLL_35XX_RATE(500000000, 250, 3, 2),
>> + PLL_35XX_RATE(400000000, 200, 3, 2),
>> + PLL_35XX_RATE(300000000, 100, 2, 2),
>> + PLL_35XX_RATE(200000000, 200, 3, 3),
>
> nit: The numbers could be aligned to the right using spaces (see exynos4.c).
>
>> + { },
>> +};
>> +
>> +static struct samsung_pll_rate_table cpll_24mhz_tbl[] __initdata = {
>> + /* sorted in descending order */
>> + /* PLL_35XX_RATE(rate, m, p, s) */
>> + PLL_35XX_RATE(666000000, 222, 4, 1),
>> + PLL_35XX_RATE(640000000, 160, 3, 1),
>> + PLL_35XX_RATE(320000000, 160, 3, 2),
>> + { },
>> +};
>> +
>> +static struct samsung_pll_rate_table dpll_24mhz_tbl[] __initdata = {
>> + /* sorted in descending order */
>> + /* PLL_35XX_RATE(rate, m, p, s) */
>> + PLL_35XX_RATE(600000000, 200, 4, 1),
>> + { },
>> +};
>> +
>> +static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
>> + /* sorted in descending order */
>> + /* PLL_36XX_RATE(rate, m, p, s, k) */
>> + PLL_36XX_RATE(600000000, 100, 2, 1, 0),
>> + PLL_36XX_RATE(400000000, 200, 3, 2, 0),
>> + PLL_36XX_RATE(200000000, 200, 3, 3, 0),
>> + PLL_36XX_RATE(180633600, 301, 5, 3, -3670),
>> + PLL_36XX_RATE( 67737600, 452, 5, 5, -27263),
>> + PLL_36XX_RATE( 49152000, 197, 3, 5, -25690),
>> + PLL_36XX_RATE( 45158401, 181, 3, 5, -24012),
>
> Have you ensured that the rates specified match the rates calculated
> using PLL equation? You can find how it is calculated in recalc_rate
> callback of this particular PLL type in clk-pll.c.
>
> As a side note, the PLL registration code should be made a bit more
> robust and just calculate the rates itself and printing warnings if they
> don't match the entered ones. I definitely need more hours in a day, so
> much to do. ;)
>
>> + { },
>> +};
>> +
>> +static struct samsung_pll_rate_table ipll_24mhz_tbl[] __initdata = {
>> + /* sorted in descending order */
>> + /* PLL_35XX_RATE(rate, m, p, s, k) */
>> + PLL_35XX_RATE(864000000, 288, 4, 1),
>> + PLL_35XX_RATE(666000000, 222, 4, 1),
>> + PLL_35XX_RATE(432000000, 288, 4, 2),
>> + { },
>> +};
>> +
>> +static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = {
>> + /* sorted in descending order */
>> + /* PLL_35XX_RATE(rate, m, p, s) */
>> + PLL_35XX_RATE(1500000000, 250, 4, 0),
>> + PLL_35XX_RATE(1400000000, 175, 3, 0),
>> + PLL_35XX_RATE(1300000000, 325, 6, 0),
>> + PLL_35XX_RATE(1200000000, 100, 2, 0),
>> + PLL_35XX_RATE(1100000000, 275, 3, 1),
>> + PLL_35XX_RATE(1000000000, 250, 3, 1),
>> + PLL_35XX_RATE(900000000, 150, 2, 1),
>> + PLL_35XX_RATE(800000000, 200, 3, 1),
>> + PLL_35XX_RATE(700000000, 175, 3, 1),
>> + PLL_35XX_RATE(600000000, 100, 2, 1),
>> + PLL_35XX_RATE(500000000, 250, 3, 2),
>> + PLL_35XX_RATE(400000000, 200, 3, 2),
>> + PLL_35XX_RATE(300000000, 100, 2, 2),
>> + PLL_35XX_RATE(200000000, 200, 3, 3),
>
> nit: Alignment.
>
> Otherwise looks good, thanks.
>
> Best regards,
> Tomasz
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