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Message-ID: <53DBA986.90705@arm.com>
Date: Fri, 01 Aug 2014 15:51:50 +0100
From: Marc Zyngier <marc.zyngier@....com>
To: Suravee Suthikulanit <suravee.suthikulpanit@....com>
CC: Mark Rutland <Mark.Rutland@....com>,
"jason@...edaemon.net" <jason@...edaemon.net>,
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Will Deacon <Will.Deacon@....com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"Harish.Kasiviswanathan@....com" <Harish.Kasiviswanathan@....com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
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Subject: Re: [PATCH 4/4 V3] irqchip: gicv2m: Add support for multiple MSI
for ARM64 GICv2m
Hi Suravee,
On 01/08/14 15:36, Suravee Suthikulanit wrote:
> On 7/30/2014 10:16 AM, Marc Zyngier wrote:
>> Why do we need this complexity at all? Is there any case where we'd want
>> to limit ourselves to a single vector for MSI?
>
> I think the ARM64 GICv2m should not be the limitation for the devices
> multiple MSI if there is no real hardware/design limitation.
>
>> arm64 is a new enough architecture so that we can expect all interrupt controllers to cope
>> with that.
>
> I am not sure if I understand this comment.
>
> We are not forcing all interrupt controllers for ARM64 to handle
> multi-MSI. They have the option to support if multi-MSI if they want
> to. I just think that we should not put the architectural limit here.
Let me be clearer: I think we should put the burden of *not* handling
multi-MSI on interrupt controllers. Here, you're making the
architectural default to be "I don't support multi-MSI", hence having to
override global vectors and such for well behaved MSI controllers like
GICv2m and GICv3 ITS.
Let's only support multi-MSI for the time being. If someone comes up
with a silly old MSI controller that can't deal with it, we'll address
the issue at that problem.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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