linux-kernel - [PATCH 6/9] Add devicetree bindings for Rockchip Soc LVDS

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Date:	Mon,  4 Aug 2014 12:53:13 +0800
From:	mark yao <yzq@...k-chips.com>
To:	heiko@...ech.de, Rob Clark <robdclark@...il.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Randy Dunlap <rdunlap@...radead.org>,
	David Airlie <airlied@...ux.ie>,
	Grant Likely <grant.likely@...aro.org>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	John Stultz <john.stultz@...aro.org>,
	Rom Lemarchand <romlem@...gle.com>
Cc:	devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
	linux-api@...r.kernel.org, olof@...om.net, djkurtz@...omium.org,
	xjq@...k-chips.com, kfx@...k-chips.com, cym@...k-chips.com,
	cf@...k-chips.com, zyw@...k-chips.com, zwl@...k-chips.com,
	xxm@...k-chips.com, huangtao@...k-chips.com,
	kever.yang@...k-chips.com, zhangqing@...k-chips.com,
	yxj@...k-chips.com, wxt@...k-chips.com, xw@...k-chips.com,
	mark yao <yzq@...k-chips.com>
Subject: [PATCH 6/9] Add devicetree bindings for Rockchip Soc LVDS

Signed-off-by: mark yao <yzq@...k-chips.com>
---
 .../devicetree/bindings/video/rockchip-panel.txt   |   30 ++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/video/rockchip-panel.txt b/Documentation/devicetree/bindings/video/rockchip-panel.txt
index 9fc200a..f599806 100644
--- a/Documentation/devicetree/bindings/video/rockchip-panel.txt
+++ b/Documentation/devicetree/bindings/video/rockchip-panel.txt
@@ -50,3 +50,33 @@ Example:
 		};
 
 	};
+
+Rockchip RK3288 LVDS interface
+================================
+Required properties:
+-compatible: "rockchip,rk3288-lvds";
+
+- reg: physical base address of the controller and length
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding: Shall be "pclk_lvds".
+	pclk_lvds: for power domain, if it disable soc will power down
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- rockchip,data-mapping: should be "vesa" or "jeida"
+	This describes how the color bits are laid out in the
+	serialized LVDS signal.
+- rockchip,data-width: should be <18> or <24>
+- rockchip,panel: required a panel node
+
+Example:
+	lvds: lvds@...6c000 {
+		compatible = "rockchip,rk3288-lvds";
+		reg = <0xff96c000 0x4000>;
+		clocks = <&cru PCLK_LVDS_PHY>;
+		clock-names = "pclk_lvds";
+
+		rockchip,grf = <&grf>;
+		rockchip,data-mapping = "jeida";
+		rockchip,data-width = <24>;
+		rockchip,panel = <&panel>;
+	};
-- 
1.7.9.5


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