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Date:	Fri, 8 Aug 2014 09:04:13 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Andi Kleen <andi@...stfloor.org>
Cc:	kan.liang@...el.com, linux-kernel@...r.kernel.org,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH] perf, x86: Fix :pp without LBR

On Thu, Aug 07, 2014 at 05:08:54PM -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@...ux.intel.com>
> 
> This fixes a side effect of Kan's earlier patch to probe the LBRs at boot
> time. Normally when the LBRs are disabled cycles:pp is disabled too.
> So for example cycles:pp doesn't work.
> 
> However this is not needed with PEBSv2 and later (Haswell) because
> it does not need LBRs to correct the IP-off-by-one.
> 
> So add an extra check for PEBSv2 that also allows :pp
> 
> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
> ---
>  arch/x86/kernel/cpu/perf_event.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
> index 2879ecd..0646d3b 100644
> --- a/arch/x86/kernel/cpu/perf_event.c
> +++ b/arch/x86/kernel/cpu/perf_event.c
> @@ -387,7 +387,7 @@ int x86_pmu_hw_config(struct perf_event *event)
>  			precise++;
>  
>  			/* Support for IP fixup */
> -			if (x86_pmu.lbr_nr)
> +			if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
>  				precise++;

Thanks
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