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Date:	Mon, 11 Aug 2014 21:27:09 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	linux-kernel@...r.kernel.org
Cc:	peterz@...radead.org, mingo@...e.hu, ak@...ux.intel.com
Subject: [PATCH v2 0/4] perf/x86: simplify PEBS event constraint management

This patchkit revamps the PEBS tables on most Intel CPUs, both simplifying
and fixing a couple of problems on Haswell processors:
 - All PEBS event supported
 - data address and data source is now reported correctly for all events

We simplify the tables by using the fact that non-PEBS event when used
in PEBS mode do not generate any PEBS records , thus they are safe to use.
This helps simplify the PEBS event constraints because they do not need
to list all suported PEBS events anymore. They only need to list
the special PEBS events, such as precise store and load latency.
This avoid some issues where the kernel is missing some PEBS events.

In V2, we cleanup some more the precise_datala() for store events.

Andi Kleen (2):
  perf/x86: Revamp PEBS event selection
  perf/x86: Don't mark DataLA addresses as store

Stephane Eranian (2):
  perf/x86: fix data source encoding issues for load latency/precise
    store
  perf/x86: code cleanups for __intel_pmu_pebs_event()

 arch/x86/include/asm/perf_event.h         |    8 ++
 arch/x86/kernel/cpu/perf_event.h          |   48 +++++++-
 arch/x86/kernel/cpu/perf_event_intel_ds.c |  183 +++++++++++------------------
 include/linux/perf_event.h                |    9 +-
 4 files changed, 129 insertions(+), 119 deletions(-)

-- 
1.7.9.5

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