linux-kernel - Re: [PATCH] perf, x86: Use extended offcore mask on Haswell

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Message-ID: <CABPqkBT++yth87P=pGcKZ_HHcd9GUxBmDinBCsV21RfFnQeVHA@mail.gmail.com>
Date:	Tue, 12 Aug 2014 08:03:58 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	Andi Kleen <andi@...stfloor.org>,
	LKML <linux-kernel@...r.kernel.org>,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH] perf, x86: Use extended offcore mask on Haswell

On Tue, Aug 12, 2014 at 7:56 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Mon, Aug 11, 2014 at 05:11:30PM -0700, Andi Kleen wrote:
>> From: Andi Kleen <ak@...ux.intel.com>
>>
>> HSW-EP has a larger offcore mask than the client Haswell CPUs.
>> It is the same mask as on Sandy/IvyBridge-EP. All of
>> Haswell was using the client mask, so some bits were missing.
>>
>> On the client parts some bits were also missing compared
>> to Sandy/IvyBridge, in particular the bits to match on a L4
>> cache hit.
>>
>> The Haswell core in both client and server incarnations
>> accepts the same bits (but some are nops), so we can use
>> the same mask.
>>
>> So use the snbep extended mask, which is a superset of the
>> client and the server, for all of Haswell.
>>
>> This allows specifying a number of extra offcore events, like
>> for example for HSW-EP.
>>
>> % perf stat -e cpu/event=0xb7,umask=0x1,offcore_rsp=0x3fffc00100,name=offcore_response_pf_l3_rfo_l3_miss_any_response/ true
>>
>> which were <not supported> before.
>>
>> v2: Post correct patch.
>> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
>
> I seem to have this patch; so that means this is a repost right?
>
Think Andi said, it was a rebase. Just found time today to test it.
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