lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <27240C0AC20F114CBF8149A2696CBE4A01E5B5FB@SHSMSX101.ccr.corp.intel.com>
Date:	Thu, 14 Aug 2014 11:17:52 +0000
From:	"Liu, Chuansheng" <chuansheng.liu@...el.com>
To:	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Peter Zijlstra <peterz@...radead.org>
CC:	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	LKML <linux-kernel@...r.kernel.org>,
	"Liu, Changcheng" <changcheng.liu@...el.com>,
	"Wang, Xiaoming" <xiaoming.wang@...el.com>,
	"Chakravarty, Souvik K" <souvik.k.chakravarty@...el.com>
Subject: RE: [PATCH] cpuidle: Fix the CPU stuck at C0 for 2-3s after PM_QOS
 back to DEFAULT



> -----Original Message-----
> From: Daniel Lezcano [mailto:daniel.lezcano@...aro.org]
> Sent: Thursday, August 14, 2014 7:15 PM
> To: Peter Zijlstra
> Cc: Liu, Chuansheng; Rafael J. Wysocki; linux-pm@...r.kernel.org; LKML; Liu,
> Changcheng; Wang, Xiaoming; Chakravarty, Souvik K
> Subject: Re: [PATCH] cpuidle: Fix the CPU stuck at C0 for 2-3s after PM_QOS
> back to DEFAULT
> 
> On 08/14/2014 01:00 PM, Peter Zijlstra wrote:
> > On Thu, Aug 14, 2014 at 12:29:32PM +0200, Daniel Lezcano wrote:
> >> Hi Chuansheng,
> >>
> >> On 14 August 2014 04:11, Chuansheng Liu <chuansheng.liu@...el.com>
> wrote:
> >>
> >>> We found sometimes even after we let PM_QOS back to DEFAULT,
> >>> the CPU still stuck at C0 for 2-3s, don't do the new suitable C-state
> >>> selection immediately after received the IPI interrupt.
> >>>
> >>> The code model is simply like below:
> >>> {
> >>>          pm_qos_update_request(&pm_qos, C1 - 1);
> >>>                  < == Here keep all cores at C0
> >>>          ...;
> >>>          pm_qos_update_request(&pm_qos,
> PM_QOS_DEFAULT_VALUE);
> >>>                  < == Here some cores still stuck at C0 for 2-3s
> >>> }
> >>>
> >>> The reason is when pm_qos come back to DEFAULT, there is IPI interrupt to
> >>> wake up the core, but when core is in poll idle state, the IPI interrupt
> >>> can not break the polling loop.
> >
> > So seeing how you're from @intel.com I'm assuming you're using x86 here.
> >
> > I'm not seeing how this can be possible, MWAIT is interrupted by IPIs
> > just fine, which means we'll fall out of the cpuidle_enter(), which
> > means we'll cpuidle_reflect(), and then leave cpuidle_idle_call().
> >
> > It will indeed not leave the cpu_idle_loop() function and go right back
> > into cpuidle_idle_call(), but that will then call cpuidle_select() which
> > should pick a new C state.
> >
> > So the interrupt _should_ work. If it doesn't you need to explain why.
> 
> I think the issue is related to the poll_idle state, in
> drivers/cpuidle/driver.c. This state is x86 specific and inserted in the
> cpuidle table as the state 0 (POLL). There is no mwait for this state.
> It is a bit confusing because this state is not listed in the acpi /
> intel idle driver but inserted implicitly at the beginning of the idle
> table by the cpuidle framework when the driver is registered.

Yes, I am talking about the poll_idle() function which didn't use the mwait,
If we want the reselection happening immediately, we need to break the poll while loop
with setting schedule bit, insteadly we didn't care if real re-schedule happening or not.




Powered by blists - more mailing lists