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Message-ID: <53F45177.9000706@redhat.com>
Date: Wed, 20 Aug 2014 09:42:47 +0200
From: Paolo Bonzini <pbonzini@...hat.com>
To: Wanpeng Li <wanpeng.li@...ux.intel.com>
CC: Jan Kiszka <jan.kiszka@...mens.com>,
Marcelo Tosatti <mtosatti@...hat.com>,
Gleb Natapov <gleb@...nel.org>, Bandan Das <bsd@...hat.com>,
Zhang Yang <yang.z.zhang@...el.com>, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4] KVM: nVMX: nested TPR shadow/threshold emulation
Il 20/08/2014 08:59, Wanpeng Li ha scritto:
>
> + /*
> + * Failing the vm entry is _not_ what the processor does
> + * but it's basically the only possibility we have.
* We could still enter the guest if CR8 load exits are
* enabled, CR8 store exits are enabled, and virtualize APIC
* access is disabled; in this case the processor would never
* use the TPR shadow and we could simply clear the bit from
* the execution control. But such a configuration is useless,
* so let's keep the code simple.
> + */
> + if (!vmx->nested.virtual_apic_page)
> + nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
I thought so, but I'm afraid it's too late to do nested_vmx_failValid
here.
Without a test case, I'd be more confident if you moved the
nested_release_page/nested_get_page to a separate function, that
nested_vmx_run calls before enter_guest_mode. The same function can
map apic_access_page too, for cleanliness. Something like this:
if (cpu_has_secondary_exec_ctrls() &&
nested_cpu_has(vmcs12,
CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
(vmcs12->secondary_vm_exec_control &
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
if (vmx->nested.apic_access_page) /* shouldn't happen */
nested_release_page(vmx->nested.apic_access_page);
vmx->nested.apic_access_page =
nested_get_page(vcpu, vmcs12->apic_access_addr);
}
if (...) {
/* do the same for virtual_apic_page if CPU_BASED_TPR_SHADOW
is set... */
/*
* Failing the vm entry is _not_ what the processor does
* but it's basically the only possibility we have.
* We could still enter the guest if CR8 load exits are
* enabled, CR8 store exits are enabled, and virtualize APIC
* access is disabled; in this case the processor would never
* use the TPR shadow and we could simply clear the bit from
* the execution control. But such a configuration is useless,
* so let's keep the code simple.
*/
if (!vmx->nested.virtual_apic_page)
return -EFAULT;
}
return 0;
...
Then nested_vmx_run can do the nested_vmx_failValid if the function returns
an error.
Paolo
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