linux-kernel - [PATCH 3/9] ARM: zynq: DT: Add DDRC node

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Date:	Wed, 20 Aug 2014 13:41:49 -0700
From:	Soren Brinkmann <soren.brinkmann@...inx.com>
To:	Michal Simek <michal.simek@...inx.com>,
	Russell King <linux@....linux.org.uk>,
	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>
Cc:	Sören Brinkmann <soren.brinkmann@...inx.com>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org, linux-pm@...r.kernel.org,
	Pawel Moll <pawel.moll@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>
Subject: [PATCH 3/9] ARM: zynq: DT: Add DDRC node

Add the DDR controller to the Zynq devicetree.

Signed-off-by: Soren Brinkmann <soren.brinkmann@...inx.com>
---
 arch/arm/boot/dts/zynq-7000.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6cc83d4c6c76..587cadcf7001 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -146,6 +146,11 @@
 			cache-level = <2>;
 		};
 
+		memory-controller@...06000 {
+			compatible = "xlnx,zynq-ddrc-a05";
+			reg = <0xf8006000 0x1000>;
+		} ;
+
 		uart0: serial@...00000 {
 			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 			status = "disabled";
-- 
2.0.1.1.gfbfc394

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