linux-kernel - Re: [V0 PATCH 0/2] AMD PVH domU support

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Message-ID: <20140822152040.70221795@mantra.us.oracle.com>
Date:	Fri, 22 Aug 2014 15:20:40 -0700
From:	Mukesh Rathor <mukesh.rathor@...cle.com>
To:	David Vrabel <david.vrabel@...rix.com>
Cc:	<boris.ostrovsky@...cle.com>, <xen-devel@...ts.xenproject.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [V0 PATCH 0/2] AMD PVH domU support

On Fri, 22 Aug 2014 14:52:41 +0100
David Vrabel <david.vrabel@...rix.com> wrote:

> On 21/08/14 03:16, Mukesh Rathor wrote:
> > Hi,
> > 
> > Here's first stab at AMD PVH domU support. Pretty much the only
> > thing needed is EFER bits set. Please review.
> 
> I'm not going to accept this until there is some ABI documentation
> stating explicitly what state non-boot CPUs will be in.
> 
> I'm particularly concerned that: a) there is a difference between AMD
> and Intel; and b) you want to change the ABI by clearing a the
> EFER.SCE bit.

Correct, I realize it changes the ABI, but I believe that is the right 
thing to do while we can, specially, since we need to fix the EFER for
NX anyways. Looking at the code, it appears this would be the final
cleanup for this ABI... :)..

However, if that's not possible, I suppose we can just leave it as is
too for the SC bit.

thanks
Mukesh
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