linux-kernel - Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

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Date:	Tue, 26 Aug 2014 11:14:14 +0100
From:	Will Deacon <will.deacon@....com>
To:	Kever Yang <kever.yang@...k-chips.com>
Cc:	Russell King <linux@....linux.org.uk>,
	Shawn Guo <shawn.guo@...aro.org>,
	Gregory CLEMENT <gregory.clement@...e-electrons.com>,
	Nicolas Pitre <nico@...aro.org>,
	Marc Carino <marc.ceeeee@...il.com>,
	Mahesh Sivasubramanian <msivasub@...eaurora.org>,
	Jonathan Austin <Jonathan.Austin@....com>,
	"heiko@...ech.de" <heiko@...ech.de>,
	"addy.ke@...k-chips.com" <addy.ke@...k-chips.com>,
	"xjq@...k-chips.com" <xjq@...k-chips.com>,
	"cf@...k-chips.com" <cf@...k-chips.com>,
	"hj@...k-chips.com" <hj@...k-chips.com>,
	"huangtao@...k-chips.com" <huangtao@...k-chips.com>,
	Ben Dooks <ben.dooks@...ethink.co.uk>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

On Mon, Aug 18, 2014 at 10:58:09AM +0100, Kever Yang wrote:
> From: Huang Tao <huangtao@...k-chips.com>
> 
> On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of
> two conditional store instructions with opposite condition code and
> updating the same register, the system might enter a deadlock if the
> second conditional instruction is an UNPREDICTABLE STR or STM
> instruction. This workaround setting bit[12] of the Feature Register
> prevents the erratum. This bit disables an optimisation applied to a
> sequence of 2 instructions that use opposing condition codes.
> 
> Signed-off-by: Huang Tao <huangtao@...k-chips.com>
> Signed-off-by: Kever Yang <kever.yang@...k-chips.com>
> ---

The Rk3288 I have advertises itself as an r0p1 Cortex-A12 CPU, so isn't
affected by this issue. Until we have an SoC supported in mainline that
requires this workaround, I don't think we should merge it.

Also, please consider setting these bits in your firmware if possible.
The feature register isn't writable from the non-secure side, so if you
want to use virtualisation you'll need to do this differently.

Will
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