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Message-ID: <53FEF325.20505@amd.com>
Date:	Thu, 28 Aug 2014 04:15:17 -0500
From:	Suravee Suthikulpanit <suravee.suthikulpanit@....com>
To:	Jingoo Han <jg1.han@...sung.com>
CC:	<marc.zyngier@....com>, <mark.rutland@....com>,
	<jason@...edaemon.net>, <pawel.moll@....com>,
	<Catalin.Marinas@....com>, <Will.Deacon@....com>,
	<tglx@...utronix.de>, <Harish.Kasiviswanathan@....com>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-doc@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X)



On 08/13/2014 09:56 PM, Jingoo Han wrote:
> On Thursday, August 14, 2014 12:01 AM, Suravee Suthikulpanit wrote:
>>
>> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
>>
>> ARM GICv2m specification extends GICv2 to support MSI(-X) with
>> a new set of register frame. This patch introduces support for
>> the non-secure GICv2m register frame. Currently, GICV2m is available
>> in certain version of GIC-400.
>>
>> The patch introduces a new property in ARM gic binding, the v2m subnode.
>> It is optional.
>
> Hi Suravee Suthikulpanit,
>
> I added some minor comments.

Thanks for the cleaning up comments.

Suravee
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