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Message-ID: <OF844FADBC.6B73E319-ONC1257D43.005106B8-C1257D43.005467D6@transmode.se>
Date: Fri, 29 Aug 2014 17:21:55 +0200
From: Joakim Tjernlund <joakim.tjernlund@...nsmode.se>
To: Christophe Leroy <christophe.leroy@....fr>
Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>,
linux-kernel@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
Paul Mackerras <paulus@...ba.org>, scottwood@...escale.com
Subject: Re: [PATCH v2 00/19] powerpc/8xx: Optimise MMU TLB handling and add support
of 16k pages
Christophe Leroy <christophe.leroy@....fr> wrote on 2014/08/29 11:13:24:
>
> This patchset:
> 1) provides several MMU TLB handling optimisation on MPC8xx.
> 2) adds support of 16k pages on MPC8xx.
> All changes have been successfully tested on a custom board equipped
with MPC885
>
> The two differences with first version of the patch are:
> 1) I removed the patch number 10, which was implementing a 16 bit
alignment of the
> PGDIR. It is not worth potentially wasting up to 64k of memory just for
removing one
> instruction (ori).
> 2) I managed to preserve r11 while calculating the level 2 address,
therefore
> no more need to save r11 into CR.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@....fr>
> Tested-by: Christophe Leroy <christophe.leroy@....fr>
This looks good but I need to look harder, some minor critique
though(already sent)
As you are optimizing I think the impl.of powerpc/8xx: Invalidate non
present TLBs
in 2.4 is better than 3.x, compare:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/powerpc/mm/fault.c?id=5efab4a02c89c252fb4cce097aafde5f8208dbfe
with
https://git.kernel.org/cgit/linux/kernel/git/wtarreau/linux-2.4.git/commit/?id=da5c5609e86fb12061f2c05a6ddd80ffc46592b2
This will free the TLB before you jump to xxx_page_fault which might need
a TLB before invalidation
and it isolates this 8xx quirk in 8xx specific code.
Jocke
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