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Message-Id: <1409683455-29168-2-git-send-email-andi@firstfloor.org>
Date: Tue, 2 Sep 2014 11:44:12 -0700
From: Andi Kleen <andi@...stfloor.org>
To: peterz@...radead.org
Cc: linux-kernel@...r.kernel.org, mingo@...nel.org, eranian@...gle.com,
tglx@...utronix.de, Andi Kleen <ak@...ux.intel.com>
Subject: [PATCH 2/5] perf, x86: Document all Haswell models
From: Andi Kleen <ak@...ux.intel.com>
Add names for each Haswell model as requested by Peter.
v2: Remove Crystall Well name.
v3: Change names
Signed-off-by: Andi Kleen <ak@...ux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index f962e26..7c9f78e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2540,10 +2540,10 @@ __init int intel_pmu_init(void)
break;
- case 60: /* 22nm Haswell */
- case 63:
- case 69:
- case 70:
+ case 60: /* 22nm Haswell Core */
+ case 63: /* 22nm Haswell Server */
+ case 69: /* 22nm Haswell ULT */
+ case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
--
1.9.3
--
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