linux-kernel - Re: [PATCH] x86, lpc, Allow only one load of lpc

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Message-ID: <1598720.9R5g9ohVoY@petert>
Date:	Wed, 03 Sep 2014 12:29:28 -0500
From:	Peter Tyser <ptyser@...-inc.com>
To:	Guenter Roeck <linux@...ck-us.net>
Cc:	Prarit Bhargava <prarit@...hat.com>,
	Lee Jones <lee.jones@...aro.org>, linux-kernel@...r.kernel.org,
	Samuel Ortiz <sameo@...ux.intel.com>
Subject: Re: [PATCH] x86, lpc, Allow only one load of lpc_ich

> > >>> Then why do they [have two devices specified]?
> > >> 
> > >> Because the vendor didn't/forgot to hide one from the kernel in BIOS --
> > >> hence FW_BUG.
> > > 
> > > If only one is useful, why have the second one in the first place?
> > 
> > That's just it -- it shouldn't have been exposed (again, according to
> > Intel).> 
> > > If the devices are present and we can see them, why not have 2?  Some
> > > users might find a use for them.
> > 
> > No one will.
> 
> Really ? I must be the "no one" then.
> 
> If available, I like using two watchdogs: One to be controlled by, say,
> systemd, one to be controlled by the watchdog daemon. If I have three, I
> might find use for it as well: One more to be controlled by whatever
> application is running on the system.
> 
> Sure, that may be considered overkill, but declaring that "no one will use
> them" if more than one watchdog is available is just not correct. After
> all, there was a _reason_ for introducing the capability to support more
> than one watchdog into the watchdog subsystem.
> 
> Similar, if there are multiple LPCs with separate GPIO pins on each in the
> system, I don't entirely understand why the GPIO pins on the second chip
> would or should be declared to be unusable. Why ?

I agree with Guenter - I'd like to support and use as many watchdogs and GPIOs 
as available.  High reliability applications often have 2 watchdogs as a data 
point, and more GPIO is always nice!

Can you give more background on your hardware and firmware setup?  Are there 
physically two ICH bridges, or just one that is showing up two times due to a 
firmware bug?  If there are two ICH bridges, how are they wired up to your CPU?  
Understanding your configuration would help others give suggestions on fixes or 
workarounds.

Regards,
Peter
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