linux-kernel - Re: [PATCH] x86, lpc, Allow only one load of lpc

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Message-ID: <20140903200811.GB7240@roeck-us.net>
Date:	Wed, 3 Sep 2014 13:08:11 -0700
From:	Guenter Roeck <linux@...ck-us.net>
To:	Peter Tyser <ptyser@...-inc.com>
Cc:	Prarit Bhargava <prarit@...hat.com>,
	Lee Jones <lee.jones@...aro.org>, linux-kernel@...r.kernel.org,
	Samuel Ortiz <sameo@...ux.intel.com>
Subject: Re: [PATCH] x86, lpc, Allow only one load of lpc_ich

On Wed, Sep 03, 2014 at 02:13:55PM -0500, Peter Tyser wrote:
> > > Can you give more background on your hardware and firmware setup?
> > 
> > Unfortunately I cannot :(  The system isn't "mine" per se.  It is (as the
> > dumps show) IBM's.
> 
> Can you look at the IBM manual and see info about which chipsets are used, and 
> how they are connected?
> 
> > Are there
> > 
> > > physically two ICH bridges, or just one that is showing up two times due
> > > to a firmware bug?
> > 
> > I can answer that.  There are two physical ICH bridges, and according to
> > Intel one should be masked off.  We shouldn't run with two.
> 
> Interesting.  The "normal" setup I'm familiar with is multiple CPUs wired up 
> to one IOH, and that IOH would be wired up to the ICH10.  There'd only be one 
> ICH10 in this configuration though.  An example is on page 30 of 
> http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/5520-5500-chipset-ioh-datasheet.pdf  I'm not sure how it'd be possible to wire up 2 
> ICH10s to one CPU?
> 
Multiple ICHs connected to multiple CPUs, maybe ?

Guenter
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