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Message-Id: <1409872109-31645-5-git-send-email-andi@firstfloor.org>
Date:	Thu,  4 Sep 2014 16:08:29 -0700
From:	Andi Kleen <andi@...stfloor.org>
To:	peterz@...radead.org
Cc:	linux-kernel@...r.kernel.org, mingo@...nel.org, eranian@...gle.com,
	tglx@...utronix.de, Andi Kleen <ak@...ux.intel.com>
Subject: [PATCH 5/5] perf, x86, uncore: Fix PCU filter setup for Sandy/Ivy/Haswell EP

From: Andi Kleen <ak@...ux.intel.com>

The PCU frequency band filters use 8 bit each in a register.
When setting up the value the shift value was not correctly
scaled, which resulted in all filters except for band 0 to
be zero. Fix the scaling.

This allows to correctly monitor multiple uncore frequency bands.

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index b237abc2..adf138e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -841,7 +841,7 @@ static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *
 	if (ev_sel >= 0xb && ev_sel <= 0xe) {
 		reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
 		reg1->idx = ev_sel - 0xb;
-		reg1->config = event->attr.config1 & (0xff << reg1->idx);
+		reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8));
 	}
 	return 0;
 }
-- 
1.9.3

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