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Message-ID: <54090AF4.7060406@hurleysoftware.com>
Date: Thu, 04 Sep 2014 20:59:32 -0400
From: Peter Hurley <peter@...leysoftware.com>
To: "H. Peter Anvin" <hpa@...or.com>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
David Laight <David.Laight@...LAB.COM>
CC: Jakub Jelinek <jakub@...hat.com>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
Tony Luck <tony.luck@...el.com>,
"linux-ia64@...r.kernel.org" <linux-ia64@...r.kernel.org>,
Oleg Nesterov <oleg@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Paul Mackerras <paulus@...ba.org>,
"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
Miroslav Franc <mfranc@...hat.com>,
Richard Henderson <rth@...ddle.net>,
linux-alpha@...r.kernel.org
Subject: Re: bit fields && data tearing
[ +cc linux-alpha ]
On 09/04/2014 06:14 PM, H. Peter Anvin wrote:
> On 09/04/2014 02:52 AM, Benjamin Herrenschmidt wrote:
>>
>> Yeah correct, alpha and bytes right ? Is there any other ? That's why I
>> suggested int.
>>
>
> Even for Alpha it is only the 21064 AFAIK.
For -mcpu=ev5 (21164) and the following test
struct x {
long a;
char b;
char c;
char d;
char e;
};
void store_b(struct x *p) {
p->b = 1;
}
gcc generates:
void store_b(struct x *p) {
0: 08 00 30 a0 ldl t0,8(a0)
4: 01 f1 3f 44 andnot t0,0xff,t0
8: 01 34 20 44 or t0,0x1,t0
c: 08 00 30 b0 stl t0,8(a0)
10: 01 80 fa 6b ret
IOW, rmw on 3 adjacent bytes, which is bad :)
For -mcpu=ev56 (21164A), the generated code is:
void store_b(struct x *p) {
0: 01 00 3f 20 lda t0,1
4: 08 00 30 38 stb t0,8(a0)
8: 01 80 fa 6b ret
which is ok.
I have no idea how prevalent the ev56 is compared to the ev5.
Still we're talking about a chip that came out in 1996.
I still hate split caches though.
Regards,
Peter Hurley
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