linux-kernel - Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

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Date:	Fri, 05 Sep 2014 08:00:14 -0600
From:	Toshi Kani <toshi.kani@...com>
To:	Andy Lutomirski <luto@...capital.net>
Cc:	Henrique de Moraes Holschuh <hmh@....eng.br>,
	"H. Peter Anvin" <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>, akpm@...uxfoundation.org,
	Arnd Bergmann <arnd@...db.de>,
	"linux-mm@...ck.org" <linux-mm@...ck.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Juergen Gross <jgross@...e.com>,
	Stefan Bader <stefan.bader@...onical.com>,
	Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
Subject: Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 17:51 -0700, Andy Lutomirski wrote:
> On Thu, Sep 4, 2014 at 5:29 PM, Toshi Kani <toshi.kani@...com> wrote:
> > On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote:
> >> On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh
> >> <hmh@....eng.br> wrote:
> >> > On Thu, 04 Sep 2014, H. Peter Anvin wrote:
> >> >> On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote:
> >> >> > I am worried of uncharted territory, here.  I'd actually advocate for not
> >> >> > enabling the upper four PAT entries on IA-32 at all, unless Windows 9X / XP
> >> >> > is using them as well.  Is this a real concern, or am I being overly
> >> >> > cautious?
> >> >>
> >> >> It is extremely unlikely that we'd have PAT issues in 32-bit mode and
> >> >> not in 64-bit mode on the same CPU.
> >> >
> >> > Sure, but is it really a good idea to enable this on the *old* non-64-bit
> >> > capable processors (note: I don't mean x86-64 processors operating in 32-bit
> >> > mode) ?
> >> >
> >> >> As far as I know, the current blacklist rule is very conservative due to
> >> >> lack of testing more than anything else.
> >> >
> >> > I was told that much in 2009 when I asked why cpuid 0x6d8 was blacklisted
> >> > from using PAT :-)
> >>
> >> At the very least, anyone who plugs an NV-DIMM into a 32-bit machine
> >> is nuts, and not just because I'd be somewhat amazed if it even
> >> physically fits into the slot. :)
> >
> > According to the spec, the upper four entries bug was fixed in Pentium 4
> > model 0x1.  So, the remaining Intel 32-bit processors that may enable
> > the upper four entries are Pentium 4 model 0x1-4.  Should we disable it
> > for all Pentium 4 models?
> 
> Assuming that this is Pentium 4 erratum N46, then there may be another
> option: use slot 7 instead of slot 4 for WT.  Then, even if somehow
> the blacklist screws up, the worst that happens is that a WT page gets
> interpreted as UC.  I suppose this could cause aliasing issues, but
> can't cause problems for people who don't use the high entries in the
> first place.

That's a fine idea, but as Ingo also suggested, I am going to disable
this feature on all Pentium 4 models.  That should give us a safety
margin.  Using slot 4 has a benefit that it keeps the PAT setup
consistent with Xen.      

Thanks,
-Toshi

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