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Message-ID: <20140905201906.GY5001@linux.vnet.ibm.com>
Date: Fri, 5 Sep 2014 13:19:06 -0700
From: "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To: Peter Hurley <peter@...leysoftware.com>
Cc: Peter Zijlstra <peterz@...radead.org>,
Michael Cree <mcree@...on.net.nz>,
"H. Peter Anvin" <hpa@...or.com>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
David Laight <David.Laight@...LAB.COM>,
Jakub Jelinek <jakub@...hat.com>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
Tony Luck <tony.luck@...el.com>,
"linux-ia64@...r.kernel.org" <linux-ia64@...r.kernel.org>,
Oleg Nesterov <oleg@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Paul Mackerras <paulus@...ba.org>,
"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
Miroslav Franc <mfranc@...hat.com>,
Richard Henderson <rth@...ddle.net>,
linux-alpha@...r.kernel.org
Subject: Re: bit fields && data tearing
On Fri, Sep 05, 2014 at 04:01:35PM -0400, Peter Hurley wrote:
> On 09/05/2014 03:52 PM, Peter Zijlstra wrote:
> > On Fri, Sep 05, 2014 at 11:31:09AM -0700, Paul E. McKenney wrote:
> >> compiler: Allow 1- and 2-byte smp_load_acquire() and smp_store_release()
> >>
> >> CPUs without single-byte and double-byte loads and stores place some
> >> "interesting" requirements on concurrent code. For example (adapted
> >> from Peter Hurley's test code), suppose we have the following structure:
> >>
> >> struct foo {
> >> spinlock_t lock1;
> >> spinlock_t lock2;
> >> char a; /* Protected by lock1. */
> >> char b; /* Protected by lock2. */
> >> };
> >> struct foo *foop;
> >>
> >> Of course, it is common (and good) practice to place data protected
> >> by different locks in separate cache lines. However, if the locks are
> >> rarely acquired (for example, only in rare error cases), and there are
> >> a great many instances of the data structure, then memory footprint can
> >> trump false-sharing concerns, so that it can be better to place them in
> >> the same cache cache line as above.
> >>
> >> But if the CPU does not support single-byte loads and stores, a store
> >> to foop->a will do a non-atomic read-modify-write operation on foop->b,
> >> which will come as a nasty surprise to someone holding foop->lock2. So we
> >> now require CPUs to support single-byte and double-byte loads and stores.
> >> Therefore, this commit adjusts the definition of __native_word() to allow
> >> these sizes to be used by smp_load_acquire() and smp_store_release().
> >
> > So does this patch depends on a patch that removes pre EV56 alpha
> > support? I'm all for removing that, but I need to see the patch merged
> > before we can do this.
>
> I'm working on that but Alpha's Kconfig is not quite straightforward.
>
>
> ... and I'm wondering if I should _remove_ pre-EV56 configurations or
> move the default choice and produce a warning about unsupported Alpha
> CPUs instead?
I suspect that either would work, given that the Alpha community is
pretty close-knit. Just setting the appropriate flag to make the
compiler generate one-byte and two-byte loads and stores would
probably suffice. ;-)
Thanx, Paul
> Regards,
> Peter Hurley
>
> [ How does one do a red popup in kbuild?
> The 'comment' approach is too subtle.
> ]
>
>
>
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