linux-kernel - [PATCH] Rockchip: RK3288: CRU: swap value of bit for CORE clock pll source selection

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <1409896166-32732-1-git-send-email-xjq@rock-chips.com>
Date:	Fri,  5 Sep 2014 13:49:26 +0800
From:	jianqun <xjq@...k-chips.com>
To:	heiko@...ech.de, mturquette@...aro.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc:	xjq@...k-chips.com, kever.yang@...k-chips.com,
	huangtao@...k-chips.com, zyw@...k-chips.com, yzq@...k-chips.com,
	zhenfu.fang@...k-chips.com, cf@...k-chips.com, kfx@...k-chips.com
Subject: [PATCH] Rockchip: RK3288: CRU: swap value of bit for CORE clock pll source selection

From: xujianqun <xjq@...k-chips.com>

For RK3288, core clock pll source select APLL when bit value is 1, select GPLL
when bit value is 0;

CRU_CLKSEL0_CON [15]
- core_clk_pll_sel
- CORE clock pll source selection
-- 1'b1: select ARM PLL
-- 1'b0: select GENERAL PLL

BUG=none
TEST= "cat /sys/kernel/debug/clk/clk_summary |grep apll" check parent of core clock

Change-Id: I44a528af256da1fad573b4ccf9d0a20ad4cf6d68
Signed-off-by: xujianqun <xjq@...k-chips.com>
---
 drivers/clk/rockchip/clk-cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index c5b14e9..1725ac7 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -136,7 +136,7 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
 	}
 
 	/* select alternate parent */
-	writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
+	writel(HIWORD_UPDATE(0, 1, reg_data->mux_core_shift),
 	       cpuclk->reg_base + reg_data->core_reg);
 
 	/* alternate parent is active now. set the dividers */
@@ -163,7 +163,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
 	spin_lock(cpuclk->lock);
 
 	/* post-rate change event, re-mux back to primary parent */
-	writel(HIWORD_UPDATE(0, 1, reg_data->mux_core_shift),
+	writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
 	       cpuclk->reg_base + RK2928_CLKSEL_CON(0));
 
 	/* remove any core dividers */
-- 
1.9.1


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/