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Message-Id: <1410344391-5675-7-git-send-email-javier.martinez@collabora.co.uk>
Date: Wed, 10 Sep 2014 12:19:50 +0200
From: Javier Martinez Canillas <javier.martinez@...labora.co.uk>
To: Kukjin Kim <kgene.kim@...sung.com>
Cc: Doug Anderson <dianders@...omium.org>,
Olof Johansson <olof@...om.net>,
Mark Brown <broonie@...nel.org>,
Naveen Krishna Chatradhi <ch.naveen@...sung.com>,
Rahul Sharma <rahul.sharma@...sung.com>,
Andreas Faerber <afaerber@...e.de>,
linux-samsung-soc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Vivek Gautam <gautam.vivek@...sung.com>,
Javier Martinez Canillas <javier.martinez@...labora.co.uk>
Subject: [PATCH v3 6/7] ARM: dts: Set i2c7 clock at 400kHz for Peach boards
The downstream ChromeOS 3.8 kernel sets the clock frequency
for the I2C bus 7 at 400kHz. Do the same change in mainline.
Suggested-by: Doug Anderson <dianders@...omium.org>
Signed-off-by: Javier Martinez Canillas <javier.martinez@...labora.co.uk>
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 1 +
arch/arm/boot/dts/exynos5800-peach-pi.dts | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index b8fea56..f247709 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -489,6 +489,7 @@
&hsi2c_7 {
status = "okay";
+ clock-frequency = <400000>;
max98090: codec@10 {
compatible = "maxim,max98090";
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 17537f0..88b3544 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -487,6 +487,7 @@
&hsi2c_7 {
status = "okay";
+ clock-frequency = <400000>;
max98091: codec@10 {
compatible = "maxim,max98091";
--
2.1.0
--
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