linux-kernel - Re: [PATCH] arm64: LLVMLinux: Fix inline arm64 assembly for use with clang

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Wed, 10 Sep 2014 19:49:50 +0200
From:	Ard Biesheuvel <ard.biesheuvel@...aro.org>
To:	Will Deacon <will.deacon@....com>
Cc:	Olof Johansson <olof@...om.net>,
	Matthew Leach <Matthew.Leach@....com>,
	Catalin Marinas <Catalin.Marinas@....com>,
	"cl@...ux.com" <cl@...ux.com>,
	Lorenzo Pieralisi <Lorenzo.Pieralisi@....com>,
	"Vijaya.Kumar@...iumnetworks.com" <Vijaya.Kumar@...iumnetworks.com>,
	"takahiro.akashi@...aro.org" <takahiro.akashi@...aro.org>,
	"mingo@...hat.com" <mingo@...hat.com>,
	"msalter@...hat.com" <msalter@...hat.com>,
	Marc Zyngier <Marc.Zyngier@....com>,
	"steve.capper@...aro.org" <steve.capper@...aro.org>,
	"a.p.zijlstra@...llo.nl" <a.p.zijlstra@...llo.nl>,
	"sandeepa.prabhu@...aro.org" <sandeepa.prabhu@...aro.org>,
	"acme@...nel.org" <acme@...nel.org>,
	Mark Charlebois <charlebm@...il.com>,
	"anderson@...hat.com" <anderson@...hat.com>,
	"cov@...eaurora.org" <cov@...eaurora.org>,
	"jays.lee@...sung.com" <jays.lee@...sung.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"srivatsa.bhat@...ux.vnet.ibm.com" <srivatsa.bhat@...ux.vnet.ibm.com>,
	Sudeep Holla <Sudeep.Holla@....com>,
	"paulus@...ba.org" <paulus@...ba.org>,
	"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>
Subject: Re: [PATCH] arm64: LLVMLinux: Fix inline arm64 assembly for use with clang

On 10 September 2014 19:38, Will Deacon <will.deacon@....com> wrote:
> On Mon, Sep 08, 2014 at 10:30:51AM +0100, Olof Johansson wrote:
>> On Fri, Sep 05, 2014 at 04:24:20PM -0700, behanw@...verseincode.com wrote:
>> > From: Mark Charlebois <charlebm@...il.com>
>> >
>> > Fix variable types for 64-bit inline assembly.
>> >
>> > This patch now works with both gcc and clang.
>> >
>> > Signed-off-by: Mark Charlebois <charlebm@...il.com>
>> > Signed-off-by: Behan Webster <behanw@...verseincode.com>
>> > ---
>> >  arch/arm64/include/asm/arch_timer.h | 26 +++++++++++++++-----------
>> >  arch/arm64/include/asm/uaccess.h    |  2 +-
>> >  arch/arm64/kernel/debug-monitors.c  |  8 ++++----
>> >  arch/arm64/kernel/perf_event.c      | 34 +++++++++++++++++-----------------
>> >  arch/arm64/mm/mmu.c                 |  2 +-
>> >  5 files changed, 38 insertions(+), 34 deletions(-)
>> >
>> > diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
>> > index 9400596..c1f87e0 100644
>> > --- a/arch/arm64/include/asm/arch_timer.h
>> > +++ b/arch/arm64/include/asm/arch_timer.h
>> > @@ -37,19 +37,23 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
>> >     if (access == ARCH_TIMER_PHYS_ACCESS) {
>> >             switch (reg) {
>> >             case ARCH_TIMER_REG_CTRL:
>> > -                   asm volatile("msr cntp_ctl_el0,  %0" : : "r" (val));
>> > +                   asm volatile("msr cntp_ctl_el0,  %0"
>> > +                           : : "r" ((u64)val));
>>
>> Ick. Care to elaborate in the patch description why this is needed with
>> LLVM? It's really messy and very annoying having to cast register values
>> every time they're passed in, instead of the compiler handling it for you.
>>
>> Is there a way to catch this with GCC? If not, I expect you to get broken
>> all the time on this by people who don't notice.
>
> Question to the clang people (Clangers?): what happens if the %0 above is
> rewritten as %x0 and the cast on val is dropped? I could stomach a change
> adding that, but it's still likely to regress without regular build testing.
>

I did a quick test with Clang, and indeed, it infers the type of
register from the size of the operand, but it also supports explicit
%x0 and %w0 casts.
So in this particular case, we could work around it in this way.

However, I think this uncovers a much more serious issue: while we
catch the problem here because msr simply does not support 32-bit
operands, most other instructions do, and we have no idea how the
Clang generated code deviates from what GCC produces. Or am I being
paranoid here?
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/