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Date: Mon, 15 Sep 2014 16:51:13 -0700 From: Andrew Bresticker <abrestic@...omium.org> To: Ralf Baechle <ralf@...ux-mips.org>, Thomas Gleixner <tglx@...utronix.de>, Jason Cooper <jason@...edaemon.net> Cc: Andrew Bresticker <abrestic@...omium.org>, Jeffrey Deans <jeffrey.deans@...tec.com>, Markos Chandras <markos.chandras@...tec.com>, Paul Burton <paul.burton@...tec.com>, Qais Yousef <qais.yousef@...tec.com>, Jonas Gorski <jogo@...nwrt.org>, John Crispin <blogic@...nwrt.org>, David Daney <ddaney.cavm@...il.com>, linux-mips@...ux-mips.org, linux-kernel@...r.kernel.org Subject: [PATCH 10/24] MIPS: sead3: Do not overlap CPU/GIC IRQ ranges In preparation for GIC IRQ domain support, assign a GIC IRQ base that does not overlap with the CPU IRQs. Note that this breaks SEAD-3 when the GIC is in EIC mode, though I'm not convinced it was working before either. It will be fixed in the following patches. Signed-off-by: Andrew Bresticker <abrestic@...omium.org> --- arch/mips/include/asm/mips-boards/sead3int.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index 6b17aaf..2320331 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -14,6 +14,6 @@ #define GIC_BASE_ADDR 0x1b1c0000 #define GIC_ADDRSPACE_SZ (128 * 1024) -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) #endif /* !(_MIPS_SEAD3INT_H) */ -- 2.1.0.rc2.206.gedb03e5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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