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Date:	Mon, 15 Sep 2014 16:51:13 -0700
From:	Andrew Bresticker <>
To:	Ralf Baechle <>,
	Thomas Gleixner <>,
	Jason Cooper <>
Cc:	Andrew Bresticker <>,
	Jeffrey Deans <>,
	Markos Chandras <>,
	Paul Burton <>,
	Qais Yousef <>,
	Jonas Gorski <>,
	John Crispin <>,
	David Daney <>,,
Subject: [PATCH 10/24] MIPS: sead3: Do not overlap CPU/GIC IRQ ranges

In preparation for GIC IRQ domain support, assign a GIC IRQ base
that does not overlap with the CPU IRQs.

Note that this breaks SEAD-3 when the GIC is in EIC mode, though
I'm not convinced it was working before either.  It will be fixed
in the following patches.

Signed-off-by: Andrew Bresticker <>
 arch/mips/include/asm/mips-boards/sead3int.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
index 6b17aaf..2320331 100644
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ b/arch/mips/include/asm/mips-boards/sead3int.h
@@ -14,6 +14,6 @@
 #define GIC_BASE_ADDR		0x1b1c0000
 #define GIC_ADDRSPACE_SZ	(128 * 1024)
 #endif /* !(_MIPS_SEAD3INT_H) */

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