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Date:	Mon, 15 Sep 2014 12:25:25 -0700
From:	Greg Kroah-Hartman <>
Cc:	Greg Kroah-Hartman <>,,
	"Aneesh Kumar K.V" <>,
	Benjamin Herrenschmidt <>
Subject: [PATCH 3.14 025/114] powerpc/thp: Add write barrier after updating the valid bit

3.14-stable review patch.  If anyone has any objections, please let me know.


From: "Aneesh Kumar K.V" <>

commit b0aa44a3dfae3d8f45bd1264349aa87f87b7774f upstream.

With hugepages, we store the hpte valid information in the pte page
whose address is stored in the second half of the PMD. Use a
write barrier to make sure clearing pmd busy bit and updating
hpte valid info are ordered properly.

Signed-off-by: Aneesh Kumar K.V <>
Signed-off-by: Benjamin Herrenschmidt <>
Signed-off-by: Greg Kroah-Hartman <>

 arch/powerpc/mm/hugepage-hash64.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

--- a/arch/powerpc/mm/hugepage-hash64.c
+++ b/arch/powerpc/mm/hugepage-hash64.c
@@ -172,8 +172,11 @@ repeat:
 		mark_hpte_slot_valid(hpte_slot_array, index, slot);
-	 * No need to use ldarx/stdcx here
+	 * The hpte valid is stored in the pgtable whose address is in the
+	 * second half of the PMD. Order this against clearing of the busy bit in
+	 * huge pmd.
+	smp_wmb();
 	*pmdp = __pmd(new_pmd & ~_PAGE_BUSY);
 	return 0;

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