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Message-ID: <54175E06.1030203@codeaurora.org>
Date: Mon, 15 Sep 2014 14:45:42 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Ulf Hansson <ulf.hansson@...aro.org>
CC: Jaehoon Chung <jh80.chung@...sung.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
linux-mmc <linux-mmc@...r.kernel.org>,
Chris Ball <chris@...ntf.net>,
Georgi Djakov <gdjakov@...sol.com>,
Asutosh Das <asutoshd@...eaurora.org>,
Venkat Gopalakrishnan <venkatg@...eaurora.org>
Subject: Re: [PATCH] mmc: sdhci-msm: Make tuning block table endian agnostic
On 09/04/14 15:01, Stephen Boyd wrote:
>
> ----8<----
> From: Stephen Boyd <sboyd@...eaurora.org>
> Subject: [PATCH] mmc: Consolidate emmc tuning blocks
>
> The same tuning block array exists in the dw_mmc h.c and sdhci-msm.c
> files. Move these into mmc.c so that they can be shared across
> drivers.
>
> Reported-by: Jaehoon Chung <jh80.chung@...sung.com>
> Signed-off-by: Stephen Boyd <sboyd@...eaurora.org>
> ---
Hi Ulf,
Can this and the previous patch be picked up for 3.18?
Thanks,
Stephen
> drivers/mmc/core/mmc.c | 32 ++++++++++++++++++++++++++++++++
> drivers/mmc/host/dw_mmc.c | 30 ------------------------------
> drivers/mmc/host/sdhci-msm.c | 38 ++++----------------------------------
> include/linux/mmc/mmc.h | 5 +++++
> 4 files changed, 41 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index 793c6f7ddb04..9608cc8a1f65 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1135,6 +1135,38 @@ bus_speed:
> return err;
> }
>
> +const u8 tuning_blk_pattern_4bit[MMC_TUNING_BLK_PATTERN_4BIT_SIZE] = {
> + 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
> + 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
> + 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
> + 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
> + 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
> + 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
> + 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
> + 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
> +};
> +EXPORT_SYMBOL(tuning_blk_pattern_4bit);
> +
> +const u8 tuning_blk_pattern_8bit[MMC_TUNING_BLK_PATTERN_8BIT_SIZE] = {
> + 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
> + 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
> + 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
> + 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
> + 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
> + 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
> + 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
> + 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
> + 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
> + 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
> + 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
> + 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
> + 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
> + 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
> + 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
> + 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
> +};
> +EXPORT_SYMBOL(tuning_blk_pattern_8bit);
> +
> /*
> * Execute tuning sequence to seek the proper bus operating
> * conditions for HS200 and HS400, which sends CMD21 to the device.
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 1ac227c603b7..f1cefdf5e2d0 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -81,36 +81,6 @@ struct idmac_desc {
> };
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> -static const u8 tuning_blk_pattern_4bit[] = {
> - 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
> - 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
> - 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
> - 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
> - 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
> - 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
> - 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
> - 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
> -};
> -
> -static const u8 tuning_blk_pattern_8bit[] = {
> - 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
> - 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
> - 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
> - 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
> - 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
> - 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
> - 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
> - 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
> - 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
> - 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
> - 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
> - 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
> - 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
> - 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
> - 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
> - 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
> -};
> -
> static inline bool dw_mci_fifo_reset(struct dw_mci *host);
> static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 5aabffc15ae8..da74c77f34cc 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -47,36 +47,6 @@
> #define CMUX_SHIFT_PHASE_SHIFT 24
> #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
>
> -static const u8 tuning_block_64[] = {
> - 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
> - 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
> - 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
> - 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
> - 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
> - 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
> - 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
> - 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
> -};
> -
> -static const u8 tuning_block_128[] = {
> - 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
> - 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
> - 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
> - 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
> - 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
> - 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
> - 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
> - 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
> - 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
> - 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
> - 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
> - 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
> - 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
> - 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
> - 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
> - 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
> -};
> -
> struct sdhci_msm_host {
> struct platform_device *pdev;
> void __iomem *core_mem; /* MSM SDCC mapped address */
> @@ -371,8 +341,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
> {
> int tuning_seq_cnt = 3;
> u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
> - const u8 *tuning_block_pattern = tuning_block_64;
> - int size = sizeof(tuning_block_64); /* Pattern size in bytes */
> + const u8 *tuning_block_pattern = tuning_blk_pattern_4bit;
> + int size = sizeof(tuning_blk_pattern_4bit);
> int rc;
> struct mmc_host *mmc = host->mmc;
> struct mmc_ios ios = host->mmc->ios;
> @@ -388,8 +358,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
>
> if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) &&
> (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) {
> - tuning_block_pattern = tuning_block_128;
> - size = sizeof(tuning_block_128);
> + tuning_block_pattern = tuning_blk_pattern_8bit;
> + size = sizeof(tuning_blk_pattern_8bit);
> }
>
> data_buf = kmalloc(size, GFP_KERNEL);
> diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
> index 64ec963ed347..cff1f2622061 100644
> --- a/include/linux/mmc/mmc.h
> +++ b/include/linux/mmc/mmc.h
> @@ -53,6 +53,11 @@
> #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
> #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
>
> +#define MMC_TUNING_BLK_PATTERN_4BIT_SIZE 64
> +#define MMC_TUNING_BLK_PATTERN_8BIT_SIZE 128
> +extern const u8 tuning_blk_pattern_4bit[MMC_TUNING_BLK_PATTERN_4BIT_SIZE];
> +extern const u8 tuning_blk_pattern_8bit[MMC_TUNING_BLK_PATTERN_8BIT_SIZE];
> +
> /* class 3 */
> #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
>
--
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