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Message-ID: <20140917023127.GA16456@dragon>
Date: Wed, 17 Sep 2014 10:31:28 +0800
From: Shawn Guo <shawn.guo@...escale.com>
To: Nicolin Chen <nicoleotsuka@...il.com>
CC: Shengjiu Wang <shengjiu.wang@...escale.com>, <timur@...i.org>,
<Li.Xiubo@...escale.com>, <lgirdwood@...il.com>,
<broonie@...nel.org>, <perex@...ex.cz>, <tiwai@...e.de>,
<alsa-devel@...a-project.org>, <linuxppc-dev@...ts.ozlabs.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ASoC: fsl_spdif: don't change the root clock rate of
spdif in driver
On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote:
> It's not supported in the clock API or just not implemented in our
> code? Can we just register a clock without CLK_SET_RATE_PARENT to
> achieve the purpose? (We are just trying to fix those PRED and PODF
> dividers when the driver calls set_rate to their GATE clock.)
It seems I misunderstood your question. Yes, if we drop flag
CLK_SET_RATE_PARENT for the gate clock in question, the rate change
request will not be propagated to upstream dividers.
Shawn
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