linux-kernel - Re: [PATCH v3 03/21] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

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Message-ID: <541BDD58.6060707@c-s.fr>
Date:	Fri, 19 Sep 2014 09:38:00 +0200
From:	leroy christophe <christophe.leroy@....fr>
To:	Joakim Tjernlund <joakim.tjernlund@...nsmode.se>
CC:	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	linux-kernel@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
	Paul Mackerras <paulus@...ba.org>, scottwood@...escale.com
Subject: Re: [PATCH v3 03/21] powerpc/8xx: exception InstructionAccess does
 not exist on MPC8xx


Le 18/09/2014 22:02, Joakim Tjernlund a écrit :
> christophe leroy <christophe.leroy@....fr> wrote on 2014/09/18 21:11:01:
>>
>> Le 18/09/2014 20:12, Joakim Tjernlund a écrit :
>>> leroy christophe <christophe.leroy@....fr> wrote on 2014/09/18
> 18:42:14:
>>>> Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
>>>>> Christophe Leroy <christophe.leroy@....fr> wrote on 2014/09/17
>>> 18:36:57:
>>>>>> Exception InstructionAccess does not exist on MPC8xx. No need to
>>> branch
>>>>> there from somewhere else.
>>>>>> Handling can be done directly in InstructionTLBError Exception.
>>>>>>
>>>>>> Signed-off-by: Christophe Leroy <christophe.leroy@....fr>
>>>>         . = 0x1200
>>>>     DataStoreTLBMiss:
>>>> @@ -477,7 +475,11 @@ DataStoreTLBMiss:
>>>>      */
>>>>         . = 0x1300
>>>>     InstructionTLBError:
>>>> -    b    InstructionAccess
>>>> +    EXCEPTION_PROLOG
>>>> +    mr    r4,r12
>>>> +    mr    r5,r9
>>>> +    /* 0x400 is InstructionAccess exception, needed by
> bad_page_fault()
>>> */
>>>> +    EXC_XFER_LITE(0x400, handle_page_fault)
>>> You should have the code in TLBMiss and have the TLBError branch there
> as
>>> that is the common case.
>> As far as I remember, I tried it already but we don't have enough space
>> in TLBmiss for that. We can only have 40 instructions.
> Do your other optimizations first, then you might have space :)
>
>

Even with the optimisation first, there is no chance to fit ITLBError 
instructions after ITLBMiss and before DTLBMiss.
After optimisation, TLBMiss goes from 0x1100 to 0x1174. TLBError goes 
from 0x1300 to 0x13b4. DTLBMiss is at 0x1200
And this is without CPU6 ERRATA. So this is hopeless I believe.

Christophe
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