linux-kernel - Re: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings

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Date:	Wed, 24 Sep 2014 20:34:14 +0200
From:	Arnd Bergmann <arnd@...db.de>
To:	Sunil Kovvuri <sunil.kovvuri@...il.com>
Cc:	LAKML <linux-arm-kernel@...ts.infradead.org>,
	Robert Richter <rric@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	linux-pci <linux-pci@...r.kernel.org>,
	Liviu Dudau <liviu.dudau@....com>,
	LKML <linux-kernel@...r.kernel.org>,
	Robert Richter <rrichter@...ium.com>,
	Sunil Goutham <sgoutham@...ium.com>
Subject: Re: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings

On Wednesday 24 September 2014 23:34:04 Sunil Kovvuri wrote:
> On Wed, Sep 24, 2014 at 9:36 PM, Arnd Bergmann <arnd@...db.de> wrote:
> > On Wednesday 24 September 2014 17:37:45 Robert Richter wrote:
> >> +               compatible = "cavium,thunder-pcie";
> >> +               device_type = "pci";
> >> +               msi-parent = <&its>;
> >> +               bus-range = <0 255>;
> >> +               #size-cells = <2>;
> >> +               #address-cells = <3>;
> >> +               reg = <0x8480 0x00000000 0 0x10000000>;  /* Configuration space */
> >> +               ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>, /* mem ranges */
> >> +                       <0x03000000 0x8300 0x00000000 0x8300 0x00000000 0x80 0x00000000>,
> >> +                       <0x03000000 0x87e0 0x00000000 0x87e0 0x00000000 0x01 0x00000000>;
> >> +        };
> >
> > If you claim the entire 0-255 bus range, I think you should also
> > specify a domain, otherwise it's not predictable which domain you
> > get.
> >
> > The interrupt-map and interrupt-map-mask properties are required for PCI,
> > otherwise you can't do LSI interrupts.
> 
> This PCI controller supports only MSIx interrupts which are edge triggered.

Interesting, so it's not PCI compliant then? I assume this will be fixed
in the production version of the silicon, right?

Having no support for interrupts mean that the majority of PCI device drivers
will fail.

> > If your hardware can support it, you should also list I/O space and prefetchable
> > memory spaces. Can you explain why you have multiple non-prefetchable ranges?
> 
> Our hardware is an ECAM based host controller and doesn't support I/O
> and prefetchable memory spaces.
> All on-board PCI devices connected to this PCI controller have fixed resources
> and doesn't have to be allocated/reassigned. Some of these devices are
> SRIOV based.

I think you need to mark the ones that are nonrelocatable with flag
0x80000000, otherwise the PCI core might decide to reassign them.

> Kernel's SRIOV (pci/iov.c) is expecting 'resource->parent' hierarchy
> to be set, otherwise doesn't
> enable SRIOV device. So, here multiple non-prefetchable ranges of root bus
> aid in resource claiming and setting res->parent hierarchy.

I don't understand. Isn't that just a bug in the code that you are working
around with the DT. Have you tried fixing the code instead?

> We do call "pci_claim_resource" in controller driver code.
> "[PATCH 1/6] pci, thunder: Add support for Thunder PCIe host controller."

My guess is that you are using the wrong interface here. Isn't the normal
request_resource() in the host driver enough?

	Arnd
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