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Message-Id: <178aa08adfcc161fbf902d6127202089e37e03dd.1411564723.git.michal.simek@xilinx.com>
Date:	Wed, 24 Sep 2014 15:18:49 +0200
From:	Michal Simek <michal.simek@...inx.com>
To:	linux-arm-kernel@...ts.infradead.org
Cc:	monstr@...str.eu, Josh Cartwright <josh.cartwright@...com>,
	Steffen Trumtrar <s.trumtrar@...gutronix.de>,
	Rob Herring <robherring2@...il.com>,
	Peter Crosthwaite <peter.crosthwaite@...inx.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Russell King <linux@....linux.org.uk>,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH] ARM: zynq: DT: Add missing address for L2 pl310

By in sync with others node and add also baseaddr
to the node name.

Signed-off-by: Michal Simek <michal.simek@...inx.com>
---

 arch/arm/boot/dts/zynq-7000.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 64caeb47bc0c..5020de584521 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -136,7 +136,7 @@
 			      <0xF8F00100 0x100>;
 		};

-		L2: cache-controller {
+		L2: cache-controller@...02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xF8F02000 0x1000>;
 			arm,data-latency = <3 2 2>;
--
1.8.2.3


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