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Message-Id: <1411573068-12952-4-git-send-email-rric@kernel.org>
Date: Wed, 24 Sep 2014 17:37:45 +0200
From: Robert Richter <rric@...nel.org>
To: Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>
Cc: Liviu Dudau <liviu.dudau@....com>, Arnd Bergmann <arnd@...db.de>,
Sunil Goutham <sgoutham@...ium.com>,
linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, Robert Richter <rrichter@...ium.com>,
devicetree@...r.kernel.org
Subject: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings
From: Sunil Goutham <sgoutham@...ium.com>
This patch adds the PCIe host controller entry for Cavium Thunder SoCs
to the devicetree. There are 4 internal PCI controllers available.
Signed-off-by: Sunil Goutham <sgoutham@...ium.com>
Signed-off-by: Robert Richter <rrichter@...ium.com>
---
arch/arm64/boot/dts/thunder-88xx.dtsi | 49 +++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/thunder-88xx.dtsi b/arch/arm64/boot/dts/thunder-88xx.dtsi
index 9cb7cf94284a..0b433b0e7af4 100644
--- a/arch/arm64/boot/dts/thunder-88xx.dtsi
+++ b/arch/arm64/boot/dts/thunder-88xx.dtsi
@@ -407,4 +407,53 @@
clock-names = "apb_pclk";
};
};
+
+ pcie0@...480,00000000 {
+ compatible = "cavium,thunder-pcie";
+ device_type = "pci";
+ msi-parent = <&its>;
+ bus-range = <0 255>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */
+ ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>, /* mem ranges */
+ <0x03000000 0x8300 0x00000000 0x8300 0x00000000 0x80 0x00000000>,
+ <0x03000000 0x87e0 0x00000000 0x87e0 0x00000000 0x01 0x00000000>;
+ };
+
+ pcie1@...490,00000000 {
+ compatible = "cavium,thunder-pcie";
+ device_type = "pci";
+ msi-parent = <&its>;
+ bus-range = <0 255>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0x8490 0x00000000 0 0x10000000>; /* Configuration space */
+ ranges = <0x03000000 0x8310 0x00000000 0x8310 0x00000000 0x00 0x10000000>, /* mem ranges */
+ <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>;
+ };
+
+ pcie2@...4a0,00000000 {
+ compatible = "cavium,thunder-pcie";
+ device_type = "pci";
+ msi-parent = <&its>;
+ bus-range = <0 255>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0x84a0 0x00000000 0 0x10000000>; /* Configuration space */
+ ranges = <0x03000000 0x8320 0x00000000 0x8320 0x00000000 0x00 0x10000000>, /* mem ranges */
+ <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x01 0x00000000>;
+ };
+
+ pcie3@...4b0,00000000 {
+ compatible = "cavium,thunder-pcie";
+ device_type = "pci";
+ msi-parent = <&its>;
+ bus-range = <0 255>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0x84b0 0x00000000 0 0x10000000>; /* Configuration space */
+ ranges = <0x03000000 0x8330 0x00000000 0x8330 0x00000000 0x00 0x10000000>, /* mem ranges */
+ <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>;
+ };
};
--
2.1.0
--
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